magic-semi 公司IC数字后端职位 （实习生，应届生，engineer和leader）
1. 实习生职位
Magic-semi JD forIntern
Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII.Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way.
RESPONSIBILITES:
1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, powerplanning, Place, CTS andRoute.
2. Work with Front-end designers to optimizetiming/area/power of the design implementation and perform static timinganalysis.
3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).
4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.
Requirements:
1.
CS/EE or background in areas related todigital or analog chip design
2.
Known of IC backend flow.
3.
Known of timing concept.
4.
Have reading and writing skills forenglish
5.
Experience in floorplan, place, cts,route, timing ,pv and power analysis and so on.
6.
Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
7.
Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
8.
Experience and knowledge about FE design(RTL code, flow) and verification is a plus.
9.
Good analytical and debugging skills.
Send your CV to hr@magic-semi.com if you are interested.
2.应届生
Magic-semi JD for NCG
Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII.Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way.
Job Title:
Intern/NCG
RESPONSIBILITES:
1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.
2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis.
3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).
4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.
Requirements:
1.
CS/EE or background in areas related todigital or analog chip design
2.
Be familiar with IC backend flow.
3.
Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
4.
Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
5.
Experience and knowledge about FE design(RTL code, flow) and verification is a plus.
6.
Good analytical and debugging skills.
Send your CV to hr@magic-semi.com if you are interested.
3. 高级工程师
Magic-semi JD forSenior Engineer
Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII.Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way.
Job Title：
Senior Engineer
RESPONSIBILITES:
1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.
2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis.
3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).
4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.
Requirements:
1.
CS/EE or background in areas related todigital or analog chip design
2.
3 year+ work experience.
3.
experience in floorplan, place, cts,route, timing ,pv and power analysis and so on.
4.
Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
5.
Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
6.
Experience and knowledge about FE design(RTL code, flow) and verification is a plus.
7.
Good analytical and debugging skills.
Send your CV to hr@magic-semi.com if you are interested.
4. leader
Magic-semi JD forLeader Engineer
Magic-semi is a new startup design servicecompany specialized in backend training, consulting and design service. In magic-semi, design experters with rich experience in advancetechnology nodes from 40nm to 14nm and can deliver complete solutionfrom netlist to GDSII.Magic-semi has good relationship with IC leadingcompany and enables our customer to achieve success in a more efficient,reliable and cost-effective way.
Job Title:
Leader Engineer
RESPONSIBILITES:
1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.
2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis.
3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).
4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.
Requirements:
1.
CS/EE or background in areas related todigital or analog chip design
2.
7 year+ work experience for IC backend.
3.
Experience in floorplan, place, cts,route, timing ,pv and power analysis and so on.
4.
Have experience for project management.
5.
Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
6.
Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
7.
Experience and knowledge about FE design(RTL code, flow) and verification is a plus.
8.
Good analytical and debugging skills.
9.
Self-motivated and good team player.
Send your CV to hr@magic-semi.com if you are interested.
公司名字不错，做啥的
哪里 的
design service
上海张江
网上都搜不到公司名字（至少敲公司名字，前几页都百度不到），须谨慎！
搞不懂需谨慎是啥意思， 有没跟你要钱什么的，我只不过发布的是招聘信息，现在公司已经有一批人了，现在继续招聘。
百度不出来是公司网站还在调试中， 另外我们注册的是中文名字，
公司中文名是实真微电子有限公司
欢迎投递简历到hr@magic-semi.com
郑重声明， magic-semi中文名上海实真微电子有限公司，不是收费培训公司，是招聘的正式员工和实习生，欢迎您的加入
之前发的帖子的楼歪了，给一些人造成了一些误解，先郑重声明：
magic-semi中文名上海实真微电子有限公司，不是收费培训公司，是招聘的正式员工和实习生，欢迎您的加入
现在还在招实习生吗?