P&r后数字版图出现大量LVS错误,会是什么原因导致的？
encounter做完后,导出gds和.v,然后用.v生成.cdl
gds streamin layout library后用CALIBRE做LVS
总共289个错误(net:71,instances:218),里面竟然有VDD,VSS的错误
我就是按一般流程做下来的,
中间会什么原因导致这么多错误?该如何改,没有头绪.
CELL COMPARISON RESULTS ( TOP LEVEL )
#######################
# ###
##INCORRECT#
# ###
#######################
Error:Different numbers of nets (see below).
Error:Different numbers of instances (see below).
Error:Connectivity errors.
Warning:Ambiguity points were found and resolved arbitrarily.
LAYOUT CELL NAME:COUNTERB
SOURCE CELL NAME:COUNTERB
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
LayoutSourceComponent Type
--------------------------
Ports:55
Nets:137173*
Instances:137128*MN (4 pins)
137128*MP (4 pins)
------------
Total Inst:274256
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
LayoutSourceComponent Type
--------------------------
Ports:55
Nets:74111*
Instances:1313MN (4 pins)
1919MP (4 pins)
11SPDW_2_1 (4 pins)
11SPUP_2_1 (4 pins)
33SMN2 (4 pins)
3537*_invb (6 pins)
10*_invx2v (4 pins)
99_nand2b (7 pins)
11_nand3b (8 pins)
33_nor2b (7 pins)
66_sdw3b (6 pins)
1010_smn2b (5 pins)
1919_sup2b (5 pins)
11_xra2b (7 pins)
------------
Total Inst:122123
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
MatchedMatchedUnmatchedUnmatchedComponent
LayoutSourceLayoutSourceType
-----------------------------------------
Ports:5500
Nets:6969542
Instances:131300MN(NHVT12LL)
191900MP(PHVT12LL)
1100SPDW_2_1
1100SPUP_2_1
3300SMN2
353502_invb
0010_invx2v
9900_nand2b
1100_nand3b
3300_nor2b
6600_sdw3b
101000_smn2b
191900_sup2b
1100_xra2b
--------------------------------
Total Inst:12112112
o Statistics:
20 layout mos transistors were reduced to 2.
18 mos transistors were deleted by parallel reduction.
2 nets were matched arbitrarily.
o Initial Correspondence Points:
Ports:VDD VSS CLK RST_N TC_B
o Ambiguity Resolution Points:
(Each one of the following objects belongs to a group of indistinguishable objects.
The listed objects were matched arbitrarily by the Ambiguity Resolution feature of LVS.
Arbitrary matching may be prevented by assigning names to these objects or to adjacent nets).
LayoutSource
------------
Nets
----
X140/12Xcount_b_reg_5_/net43
X139/12Xcount_b_reg_0_/net43
问题不大，就是几个net， instance没对上，
port都已经对上了
开了 layout case yes
source case yes
lvs compare case names
么
应该不是你们说的大小写的问题,
我试了.
我总觉会不会是库的问题,或是别的啥.
根据提示,是schemtic里面的net多了,VDD, VSS都有问题
schmatic netlist:
v2lvs -v *_pr.v -o *_pr.cdl -l smicc65.v -s smic65.cdl -s1 VDD -s0 VSS
gds map file
M1NET610
M1SPNET610
M1VIA610
M1FILL610
M1PIN610
NAMEM1/PIN1410
V1VIA700
M2NET620
M2SPNET620
M2VIA620
M2FILL620
M2PIN620
NAMEM2/PIN1420
V2VIA710
M3NET630
M3VIA630
M3SPNET630
M3FILL630
M3PIN630
NAMEM3/PIN1430
V3VIA720
M4NET640
M4VIA640
M4SPNET640
M4FILL640
M4PIN640
NAMEM4/PIN1440
V4VIA730
M5NET650
M5VIA650
M5SPNET650
M5FILL650
M5PIN650
NAMEM5/PIN1450
V5VIA740
M6NET660
M6VIA660
M6SPNET660
M6FILL660
M6PIN660
NAMEM6/PIN1460
TV1VIA1210
TM1NET1200
TM1VIA1200
TM1SPNET1200
TM1FILL1200
TM1PIN1200
NAMETM1/PIN1260
TV2VIA1230
TM2NET1220
TM2VIA1220
TM2SPNET1220
TM2FILL1220
TM2PIN1220
NAMETM2/PIN110
找到问题了,
出在smic65.cdl
这是我从smim65.cdl 随便拿的一个:
****Sub-Circuit for HVT_INHDV20, Tue Dec 28 09:37:20 CST 2010****
.SUBCKT HVT_INHDV20 I ZN VDD VSS
MMN1 ZN I VSS VPW NHVT12LL W=2.8u L=60.00n
MMP1 ZN I VDD VNW PHVT12LL W=4.0u L=60.00n
.ENDS HVT_INHDV20
里面的VPW(衬底),VNW(nwell电位)不知道接啥,其实应该是
VNW=VDD,VPW=VSS
我现在的做法是把SMIC65.cdl里面的VNW和VPW都全换成VDD 或 VSS了.
这个在做V2LVS时有别的解决办法吗?我不想改原始库.
这个应该是 带tapcell的 设计吧，
tapcell 把VNW/VPW tap到VDD/VSS的，看看有没有erc error，说floating nwell/pwell ,
smic65.cdl里面有global VNW VPW 么?
这个VNW,VPW就是nwell，psub的电位啊
是加了welltap cell
那你就在生成的网表里面加
*.equiv VDD=VNW VSS=VPW
忘记前面有没有*了，自己试一下吧
似乎在spice netlist里给std cell加VNW=VDD VSS=VPW也能解决。
不过小编你改了welltap就解决问题了吗?我还是有一堆看不懂的incorrect nets/instances
我想请问小编layout case yessource case yes
是什么意思?在哪里可以设置吗?
我现在出现电路的网表不区分大小写的问题，比如n22与N22两条net会认为接在一起了，该怎么办?急求答案
在lvs的rule里面，找到这句话（你直接搜索大写的CASE）。改成YES或者NO