一个模块（RTL级）做成硬核的大体流程是什么？顶层如何调用硬核？

1. pin location finalized for this block
2. block level place&route, floorplan ,
3. timing driven flow till gds2 , postroute
4. extract interface model or extracted timing modelfor tihs block
so top level can use ETM/ILM ,
5. block level output lef (abstract view) for top level ,
top level instanialize the block in verilogvia pin connections ,