how to handle the virtual clocks in the backend flow？

Morning everyone,
supposing I have some virtual clocks in my design, which are used to constraint the paths on the boundary.
During CTS, I do nothing on these virtual clocks, and balanced the inter_clock_delay after CTS, and I wonder how should I balance the inter_clock_delay after CTS, expecially those in different clock domains, eg, launched by a virtual clock, but captured by a real clock, or vice versa. Now, I simply use balance_inter_clock_delay to balance the virtual clock and real clocks, resulting in some hold violations which are not easy to handle with.
In addition, if I used the blanced_inter_clock_delay in ICC, what should I do when doing signoff_STA for these virtual clocks, where the clock network delay is still an ideally-estimated value?
thanks in advance,
regards,
henry

应该不需要平衡virtual clock与 real clock；但是virtual应该设置一个合适的值。对于real clock，应该是根据实际情况做balance

set_inter_clock_delay_options -fromreal_clock -to virtual_clock
actually， virtual clock is to constraints IO PATH only ,after CTS ,should annotate the
clocktree latency onto it , use set_inter_clock_delay_options to show the relation between real
and virtual clocks , then useupdate_io_latencytoupate them ,
in fact , can no use of virtual clock to constrain IO , use real clocks also can be feasible ,