virtual flat placement该如何翻译？这个名字反映了该步骤的什么特点？

估计是floorplan/partition时用的
工具在内部把netlist打平，做一个placement

Virtual flat placement is the simultaneous placement of standard cells and macros for the whole chip
This placement is “virtual” because it temporarily considers the design to be entirely flat, without hierarchy. After you decide on the shapes and locations of the physical blocks, you restore the design hierarchy and proceed with the block-by-block physical design flow.