LVS时出现的错误
**************************************************************************************************************
INCORRECT INSTANCES
DISC#LAYOUT NAMESOURCE NAME
**************************************************************************************************************
3(S(GP)2)** missing gate **
Transistors:
X11/X44(299.240,450.930)GP
X11/X45(300.340,450.930)GP
--------------------------------------------------------------------------------------------------------------
4(S(GP)2)** missing gate **
Transistors:
X11/X58(387.430,450.730)GP
X11/X60(388.530,450.730)GP
--------------------------------------------------------------------------------------------------------------
5(S(GP)2)** missing gate **
Transistors:
X11/X68(417.400,447.010)GP
X17/X82/X34/X1/X1/X1/X0(241.720,595.000)GP
--------------------------------------------------------------------------------------------------------------
6(S(GP)2)** missing gate **
Transistors:
X11/X72/X0(407.380,447.010)GP
X11/X73/X0(408.980,447.010)GP
--------------------------------------------------------------------------------------------------------------
7(S(GP)2)** missing gate **
Transistors:
X17/X15(264.220,561.250)GP
X17/X82/X33/X1/X1/X1/X0(241.720,567.800)GP
--------------------------------------------------------------------------------------------------------------
8(S(GP)2)** missing gate **
Transistors:
X18/X45(200.510,356.880)GP
X18/X41(213.685,348.380)GP
--------------------------------------------------------------------------------------------------------------
9(S(GP)2)** missing gate **
Transistors:
X21/X71/X0(272.290,31.690)GP
X21/X44/X0(272.290,37.690)GP
--------------------------------------------------------------------------------------------------------------
10(S(GP)2)** missing gate **
Transistors:
X21/X72/X0(260.690,31.690)GP
X21/X45/X0(260.690,37.690)GP
--------------------------------------------------------------------------------------------------------------
11(S(GP)2)** missing gate **
Transistors:
X21/X73/X0(249.890,31.690)GP
X21/X46/X0(249.890,37.690)GP
--------------------------------------------------------------------------------------------------------------
12** missing gate **(SUP2)
Transistors:
XI23/XI140/XM5GP
XI23/XI140/XM0GP
--------------------------------------------------------------------------------------------------------------
13** missing gate **(SUP2)
Transistors:
XM5==4GP
XM4GP
--------------------------------------------------------------------------------------------------------------
14** missing gate **(SUP2)
Transistors:
XI61/XP167==12GP
XI61/XP196==12GP
--------------------------------------------------------------------------------------------------------------
15** missing gate **(SUP2)
Transistors:
XI79/XI6/XM52GP
XI79/XI6/XM56GP
--------------------------------------------------------------------------------------------------------------
16** missing gate **(SUP2)
Transistors:
XI79/XI6/XM49GP
XI79/XI6/XM48GP
--------------------------------------------------------------------------------------------------------------
17** missing gate **(SUP2)
Transistors:
XI79/XI6/XM38GP
XI79/XI6/XM37GP
--------------------------------------------------------------------------------------------------------------
18** missing gate **(SUP2)
Transistors:
XI79/XI59/XM0==2GP
XI79/XI59/XP31==4GP
--------------------------------------------------------------------------------------------------------------
19** missing gate **(SUP2)
Transistors:
XI23/XX561/XI8/XM6GP
XI23/XX561/XI8/XM7GP
--------------------------------------------------------------------------------------------------------------
20** missing gate **(SUP2)
Transistors:
XI23/XX558/XI8/XM6GP
XI23/XX558/XI8/XM7GP
详细点呗
像是管子没有识别到?
详细点吧。还有这是什么工具做的啊?
HHNEC的CD350工艺，calibre
net list 抓出來 是 SUP2
layout 抓出來是 SGP2
有可能 type 錯了 或是 layout 上 layer 有錯或有少
導致認成 其他 device
把另一段 寫 device 數量 unmatch 的部份
舖上來看看
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
LayoutSourceComponent Type
--------------------------
Nets:249203*
Instances:292163*M (4 pins)
479428*GP (5 pins)
88Q (3 pins)
3316*C (2 pins)
9831*R (2 pins)
11D (2 pins)
6755*NH (5 pins)
------------
Total Inst:978702
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
LayoutSourceComponent Type
--------------------------
Nets:146146
Instances:114114M (4 pins)
124124GP (5 pins)
88Q (3 pins)
1313C (2 pins)
1616R (2 pins)
11D (2 pins)
55NH (5 pins)
09*SUP2 (3 pins)
90*S(GP)2 (4 pins)
1212SM2 (4 pins)
11SM3 (5 pins)
------------
Total Inst:303303
* = Number of objects in layout different from number in source.
这9个器件和版图其它地方的器件画法都是一样的，就不明白单单这9个不识别
如果是type问题mos还是会match的，只是会提示bad component subtype
如果是type的问题，还是会match的，只是会有bad component subtype提示
管子画的应该没有问题，还是仔细的看看连接关系有啥错误，这个要耐心
09*SUP2 (3 pins)
90*S(GP)2 (4 pins)
SUP2 3个pin，S(GP)2 4个pin
应该是layer问题导致认成另一种pin个数不一样的管子
或是rule认法的问题?
同意下列這各看法 , 看看是不是有整片的 layer 造成
不同的辨識 , 也檢查接線是否有錯
09*SUP2 (3 pins)
90*S(GP)2 (4 pins)
SUP2 3个pin，S(GP)2 4个pin
应该是layer问题导致认成另一种pin个数不一样的管子
另外各个子模块单独LVS都能通过，但整体却会报这样的错了
把网表发上来看看
也有可能 是接錯 造成 辨識錯誤
SUP2 3个pin，S(GP)2 4个pin
應該都不是 mos level圖不大的話
用 flat 模式run 看看 report 有何不同
flat模式与hierarchical结果一样
把網表 相關的部份 放上來看看 (不用全部)
找一下 rule 有關 SUP2 3个pin，S(GP)2 4个pin
的部份 放上來看看
方便的話 把 rule file 和 lvs report 寄到我信箱
來遠端 lvs debug
我的e-mailmotofatfat@yahoo.com.tw
已发你邮箱~
有看了lvs report 不全
可能是 接線 錯誤
查看看 rule file 和 netlist上
GP 是 如何形成的