KT猎头代招-Principal Product Engineer--DDR IP
时间：12-12
整理：3721RD
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欧美半导体公司招聘Principal Product Engineer， 需要对DDR很有经验，工作地点在上海，有兴趣的朋友请和我联系raymond-chen@kthr.com。
Principal Product Engineer-----DDR IP
Position Description:
Our client is looking for an individual to work in design IP team. The group provides configurable DDR memory controller and PHY IP for ASICs. The job will be mainly focused on providing post technical support to customers; however there will be a variety of other engineering tasks that will allow the candidate to expand skills and responsibilities.
Provide technical support to customers for integration of IP into ASICs including:
- Debugging of customers’ simulation or silicon issues.
- Reviewing of customers’ design integration of our IPs.
- Reviewing static timing reports to assist with customers’ timing closure.
- Answering technical questions about IP operation.
- Train field engineers in IP operation.
- Interface with the R&D Team to bridge product improvements and resolve customer issues.
Position Requirements:
- Excellent oral and written communication
- Good English communication skill
- BS 8+ years of prior work-experience or MS 6+ years of prior work-experience
- All front-end skills – RTL design & verification in Verilog, synthesis, static-timing analysis, DFT
- Back-end skills – place & route, physical verification, timing closure
- Time management skills sufficient to balance multiple high-priority projects.
- Willingness to learn new skills and perform tasks that often go outside area of current expertise.
Additional Desirable Qualifications:
- Experience with Static Timing scripts and report analysis
- Familiarity with DDR memory operation, system applications, AXI, OCP, AHB
- Familiarity with Frame maker
- Scripting – in Perl, TCL, etc..
Principal Product Engineer-----DDR IP
Position Description:
Our client is looking for an individual to work in design IP team. The group provides configurable DDR memory controller and PHY IP for ASICs. The job will be mainly focused on providing post technical support to customers; however there will be a variety of other engineering tasks that will allow the candidate to expand skills and responsibilities.
Provide technical support to customers for integration of IP into ASICs including:
- Debugging of customers’ simulation or silicon issues.
- Reviewing of customers’ design integration of our IPs.
- Reviewing static timing reports to assist with customers’ timing closure.
- Answering technical questions about IP operation.
- Train field engineers in IP operation.
- Interface with the R&D Team to bridge product improvements and resolve customer issues.
Position Requirements:
- Excellent oral and written communication
- Good English communication skill
- BS 8+ years of prior work-experience or MS 6+ years of prior work-experience
- All front-end skills – RTL design & verification in Verilog, synthesis, static-timing analysis, DFT
- Back-end skills – place & route, physical verification, timing closure
- Time management skills sufficient to balance multiple high-priority projects.
- Willingness to learn new skills and perform tasks that often go outside area of current expertise.
Additional Desirable Qualifications:
- Experience with Static Timing scripts and report analysis
- Familiarity with DDR memory operation, system applications, AXI, OCP, AHB
- Familiarity with Frame maker
- Scripting – in Perl, TCL, etc..