KT猎头代招-Experienced Digital Designer
时间：12-12
整理：3721RD
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知名芯片设计公司招聘 Digital Designer，公司以模拟见长，此职位主要做数模混合相关的数字部分，需要懂数字信号处理相关的知识，请有兴趣的朋友和我联系，谢谢！
Email;raymond-chen@kthr.com
MSN:utopia.chen@hotmail.com
Position: Experienced Digital Designer
Location: Beijing, China
Responsibility:
Participate in mix-signal IC development high speed mix signal products, working with multi-site engineers on different functions such as analog design, application, product evaluation and layout. The candidate is expected to contribute to signal chain understanding/partition, design, verification, synthesis, timing and power analysis. And he/she is also required be able to understand input from application engineers to translate real word issues to design requirements. Some basic lab skill to work with product evaluation engineers and understand real silicon issue is also desired.
Requirement:
? MSEE or PHD in EE related majors
? 4-10 years working experience on RTL related design, verification and physical implementation for FPGA or ASIC.
? Be able to working with team mates to handel digital design from product concept to GDSII on each key task node, and have expereince on real silicon debug and probe.
? The candidate should have basic idea on sampling theory and digital signal processing. Basic analog understanding with real mixed signal ASIC experience is preferred. High speed design experience is a good plus but not a must.
? Self motivation, result oriented, good team work and communication skills.
? Good spoken and written English
? Supervision skill and project leader expereince is also required.
Email;raymond-chen@kthr.com
MSN:utopia.chen@hotmail.com
Position: Experienced Digital Designer
Location: Beijing, China
Responsibility:
Participate in mix-signal IC development high speed mix signal products, working with multi-site engineers on different functions such as analog design, application, product evaluation and layout. The candidate is expected to contribute to signal chain understanding/partition, design, verification, synthesis, timing and power analysis. And he/she is also required be able to understand input from application engineers to translate real word issues to design requirements. Some basic lab skill to work with product evaluation engineers and understand real silicon issue is also desired.
Requirement:
? MSEE or PHD in EE related majors
? 4-10 years working experience on RTL related design, verification and physical implementation for FPGA or ASIC.
? Be able to working with team mates to handel digital design from product concept to GDSII on each key task node, and have expereince on real silicon debug and probe.
? The candidate should have basic idea on sampling theory and digital signal processing. Basic analog understanding with real mixed signal ASIC experience is preferred. High speed design experience is a good plus but not a must.
? Self motivation, result oriented, good team work and communication skills.
? Good spoken and written English
? Supervision skill and project leader expereince is also required.