port load cap计算的问题

timing的报表如下：
****************************************
Report : timing
    -path_type full
    -delay_type max
    -input_pins
    -nets
    -max_paths 1
    -capacitance
Design : top_pad
Version: B-2008.12-SP3
Date   : Mon Jul  4 21:48:43 2011
****************************************
  Startpoint: top_core/sdr_ctr2/sdr_sel_d_reg
               (rising edge-triggered flip-flop clocked by pll_out)
  Endpoint: sdr_dq_p[0]
               (output port clocked by pll_out)
  Path Group: pll_out
  Path Type: max
  Point                                  Fanout    Cap       Incr       Path
  -----------------------------------------------------------------------------
  clock pll_out (rise edge)                                  0.00       0.00
  clock network delay (ideal)                                4.00       4.00
  top_core/sdr_ctr2/sdr_sel_d_reg/CK (DFFSQX2M)              0.00       4.00 r
  top_core/sdr_ctr2/sdr_sel_d_reg/Q (DFFSQX2M)               0.81 *     4.81 f
  top_core/sdr_ctr2/sdr_sel_d (net)         2     0.03
  top_core/sdr_ctr2/sdr_sel_d (sdr_ctr_0)                    0.00 *     4.81 f
  top_core/n27 (net)
  top_core/U24/A (BUFX2M)                                    0.00 *     4.81 f
  top_core/U24/Y (BUFX2M)                                    0.34 *     5.15 f
  top_core/sdr_sel_dq (net)                 4     0.05
  top_core/sdr_sel_dq (top_core)                             0.00 *     5.15 f
  sdr_sel_dq (net)
  U57/A (BUFX2M)                                             0.00 *     5.15 f
  U57/Y (BUFX2M)                                             0.40 *     5.55 f
  n58 (net)                                 5     0.06
  U55/A (BUFX2M)                                             0.00 *     5.55 f
  U55/Y (BUFX2M)                                             0.30 *     5.85 f
  n50 (net)                                 2     0.03
  U39/A (BUFX2M)                                             0.00 *     5.85 f
  U39/Y (BUFX2M)                                             0.64 *     6.49 f
  n49 (net)                                 2     0.16
  pad12/OEN (PB8)                                            0.00 *     6.49 f
  pad12/PAD (PB8)                                            0.94 *     7.43 r
  sdr_dq_p[0] (net)                         1    12.38
  sdr_dq_p[0] (inout)                                        0.00       7.44 r
  data arrival time                                                     7.44
  clock pll_out (rise edge)                                 10.00      10.00
  clock network delay (ideal)                                4.00      14.00
  clock uncertainty                                         -0.30      13.70
  output external delay                                     -4.00       9.70
  data required time                                                    9.70
  -----------------------------------------------------------------------------
  data required time                                                    9.70
  data arrival time                                                    -7.44
  -----------------------------------------------------------------------------
  slack (MET)                                                           2.26
1
上面的STA报表中，sdr_dq_p[0] (net) 电容为12.38，其中set_load设置了8，PB8/PAD自身的电容为4.37，剩下的0.01是怎么来的？在design的所有output port均有这个0.01不知道是怎么加上去的?有什么命令可以查看这个计算过程吗？或者可以解释这个0.01的出处？多谢！