port load cap计算的问题

这个是增加参数精度后的report:
****************************************
Report : timing
    -path_type full
    -delay_type max
    -input_pins
    -nets
    -max_paths 1
    -capacitance
Design : top_pad
Version: B-2008.12-SP3
Date   : Tue Jul  5 09:41:31 2011
****************************************
  Startpoint: top_core/sdr_ctr2/sdr_sel_d_reg
               (rising edge-triggered flip-flop clocked by pll_out)
  Endpoint: sdr_dq_p[0]
               (output port clocked by pll_out)
  Path Group: pll_out
  Path Type: max
  Point                                  Fanout    Cap       Incr       Path
  -----------------------------------------------------------------------------
  clock pll_out (rise edge)                              0.0000000000
                                                                    0.0000000000
  clock network delay (ideal)                            4.0000000000
                                                                    4.0000000000
  top_core/sdr_ctr2/sdr_sel_d_reg/CK (DFFSQX2M)          0.0000000000
                                                                    4.0000000000 r
  top_core/sdr_ctr2/sdr_sel_d_reg/Q (DFFSQX2M)           0.8099999428 *
                                                                    4.8099999428 f
  top_core/sdr_ctr2/sdr_sel_d (net)         2 0.0252410993
  top_core/sdr_ctr2/sdr_sel_d (sdr_ctr_0)                0.0000000000 *
                                                                    4.8099999428 f
  top_core/n27 (net)
  top_core/U24/A (BUFX2M)                                0.0000000000 *
                                                                    4.8099999428 f
  top_core/U24/Y (BUFX2M)                                0.3399999142 *
                                                                    5.1499996185 f
  top_core/sdr_sel_dq (net)                 4 0.0513681993
  top_core/sdr_sel_dq (top_core)                         0.0000000000 *
                                                                    5.1499996185 f
  sdr_sel_dq (net)
  U57/A (BUFX2M)                                         0.0000000000 *
                                                                    5.1499996185 f
  U57/Y (BUFX2M)                                         0.4010000229 *
                                                                    5.5509996414 f
  n58 (net)                                 5 0.0642102510
  U55/A (BUFX2M)                                         0.0000000000 *
                                                                    5.5509996414 f
  U55/Y (BUFX2M)                                         0.2990000248 *
                                                                    5.8499994278 f
  n50 (net)                                 2 0.0256840996
  U39/A (BUFX2M)                                         0.0000000000 *
                                                                    5.8499994278 f
  U39/Y (BUFX2M)                                         0.6440000534 *
                                                                    6.4939994812 f
  n49 (net)                                 2 0.1640000939
  pad12/OEN (PB8)                                        0.0000000000 *
                                                                    6.4939994812 f
  pad12/PAD (PB8)                                        0.9409999847 *
                                                                    7.4349994659 r
  sdr_dq_p[0] (net)                         1 12.3800001144
  sdr_dq_p[0] (inout)                                    0.0000226498
                                                                    7.4350223541 r
  data arrival time                                                 7.4350223541
  clock pll_out (rise edge)                              10.0000000000
                                                                    10.0000000000
  clock network delay (ideal)                            4.0000000000
                                                                    14.0000000000
  clock uncertainty                                      -0.3000000119
                                                                    13.6999998093
  output external delay                                  -4.0000000000
                                                                    9.6999998093
  data required time                                                9.6999998093
  -----------------------------------------------------------------------------
  data required time                                                9.6999998093
  data arrival time                                                 -7.4350223541
  -----------------------------------------------------------------------------
  slack (MET)                                                       2.2649774551
1
怎么看出来多余的0.01pf的出处？