Bandwidth of PLL close-loop
时间：12-11
整理：3721RD
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Q:
A frequency synthesizer with 0.1% accurate settling time of 10u sec.
PLL is 2nd-poles and DC and a zero
PLL loop hase Phase Margin of 60 Degree
Estimate the PLL close-loop bandwidth=?
Answer: 6.7 * T =10u sec, BW=1/2*Pi*T =111k Hz
Where is the 6.7 comes from ?
Thank you
A frequency synthesizer with 0.1% accurate settling time of 10u sec.
PLL is 2nd-poles and DC and a zero
PLL loop hase Phase Margin of 60 Degree
Estimate the PLL close-loop bandwidth=?
Answer: 6.7 * T =10u sec, BW=1/2*Pi*T =111k Hz
Where is the 6.7 comes from ?
Thank you
It's estimated, sometimes we use 4*T=settle time
estimate? is there any standard for it ?
thank you.
建立时间
Vout=Vin(1-exp(-t/T))，T=RC
0.1%误差：Vout/Vin=1-0.1%
可以解得：
t=1n(1/0.1%)*T=6.9*T
一般直接用7倍，这里你用6.7倍也没问题
这种ans不准确,60deg相位裕度没用到，以下进行精确计算（E为damp factor,Wn自然带宽,Wop0db为开环0dB带宽，fcl-3dB和Wcl-3dB为所求闭环带宽，Wz为零点位置）:
1. Tset = 1/(E*Wn) -> E*Wn = 1/(10u/6.7) = 0.67M
2. PM=60deg -> Wop0db = 3.3Wz = 4E*E*Wz -> E=sqrt(3.3/4)=0.91
3. use 1 and 2 -> Wn = 0.74M
4. Wcl-3dB = sqrt[1+2E*E+sqrt(2+4*E*E+4*E*E*E*E)]*Wn = 1.72M
5. fcl-3dB = Wcl-3dB/2pi = 270kHz
一般直接用7近似就可以了，这种近似只能适用足够稳定系统，
所以条件里才有60度的phase margin。
嗯，工程上这么估计没错，不过我们也要追求下理论的嘛，这样结论才更河蟹