请问STA中正负hold time的问题

请问同一设计中的不同寄存器为什么会出现正负的hold time？例如下面两个针对最短路径（min）的分析，第一个hold time为正，貌似正确；第二个hold time为负，一般是什么原因造成的？是否正常？
  Point                                                   Incr       Path
  ------------------------------------------------------------------------------
  clock dsp_clk (rise edge)                               0.00       0.00
  clock network delay (propagated)                        3.21       3.21
  dsp_ram/CORE/ALU/PDB2_DFF/ff8_8_5_/CK (DFFXL)           0.00       3.21 r
  dsp_ram/CORE/ALU/PDB2_DFF/ff8_8_5_/QN (DFFXL)           0.21 &     3.42 r
  dsp_ram/CORE/ALU/PDB2_DFF/ff8_8_5_ASTfhInst12671/Y (DLY4X1)
                                                          0.50 &     3.93 r
  dsp_ram/CORE/ALU/PDB2_DFF/ff8_8_5_ASTfhInst14960/Y (CLKBUFX2)
                                                          0.07 &     4.00 r
  dsp_ram/CORE/ALU/PDB2_DFF/mux_13/Y (OAI2BB2X1)          0.04 &     4.04 f
  dsp_ram/CORE/ALU/PDB2_DFF/ff8_8_5_/D (DFFXL)            0.00 &     4.04 f
  data arrival time                                                  4.04
  clock dsp_clk (rise edge)                               0.00       0.00
  clock network delay (propagated)                        3.21       3.21
  dsp_ram/CORE/ALU/PDB2_DFF/ff8_8_5_/CK (DFFXL)                      3.21 r
  library hold time                                       0.01       3.22
  data required time                                                 3.22
  ------------------------------------------------------------------------------
  data required time                                                 3.22
  data arrival time                                                 -4.04
  ------------------------------------------------------------------------------
  slack (MET)                                                        0.82
  Point                                                   Incr       Path
  ------------------------------------------------------------------------------
  clock dsp_clk (rise edge)                               0.00       0.00
  clock network delay (propagated)                        3.21       3.21
  dsp_ram/CORE/ALU/PDB2_DFF/ff8_8_0_/CK (EDFFTRX1)        0.00       3.21 r
  dsp_ram/CORE/ALU/PDB2_DFF/ff8_8_0_/Q (EDFFTRX1)         0.15 &     3.36 f
  dsp_ram/CORE/ALU/PDB2_DFF/q[8] (alu_struc_DW03_reg_s_pl_6)
                                                          0.00 &     3.36 f
  dsp_ram/CORE/ALU/ff8_8_0_ASTfhInst14306/Y (BUFX4)       0.13 &     3.49 f
  dsp_ram/CORE/ALU/ff8_8_0_ASTfhInst16187/Y (CLKBUFX2)    
                                                          0.09 &     3.57 f
  dsp_ram/CORE/ALU/PDB3_DFF_ff_8/D (DFFTRX1)              0.00 &     3.57 f
  data arrival time                                                  3.57
  
  clock dsp_clk (rise edge)                               0.00       0.00
  clock network delay (propagated)                        3.21       3.21
  dsp_ram/CORE/ALU/PDB3_DFF_ff_8/CK (DFFTRX1)                        3.21 r
  library hold time                                      -0.10       3.11
  data required time                                                 3.11
  ------------------------------------------------------------------------------
  data required time                                                 3.11
  data arrival time                                                 -3.57
  ------------------------------------------------------------------------------
  slack (MET)                                                        0.46