请教关于dc综合的问题
时间：10-02
整理：3721RD
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大家好，我在做一个I2C总线控制器的从机设计，正在进行DC的综合，但是约束不是很清楚怎么加。
我的输入是sclbufferi sdabufferi reset 输出是 sdabuffero
这是我整个的流程 请熟悉DC的同志看看，究竟是哪里不对啊 谢谢了。
Starting shell in XG mode...
Initializing gui preferences from file /home/user/.synopsys_dv_prefs.tcl
design_vision-xg-t> gui_start
design_vision-xg-t> #STEP1 set libraries for design #
set search_path [list /home/user/lib/aci/sc-x/synopsys /home/user/lib/aci/sc-x/symbols/synopsys
$search_path]
set link_library [list "*" ss_1v62_125c.db tt_1v8_25c.db ff_1v98_m40c.db]
set target_library [list ss_1v62_125c.db]
set symbol_library [list csm18ull.sdb]
set synthetic_library [list standard.sldb]
standard.sldb
design_vision-xg-t> #STEP2 add your v
read_file -format verilog {/home/user/Desktop/slavecode.v}
Loading db file '/home/user/lib/aci/sc-x/synopsys/ss_1v62_125c.db'
Loading db file '/home/user/lib/aci/sc-x/synopsys/tt_1v8_25c.db'
Loading db file '/home/user/lib/aci/sc-x/synopsys/ff_1v98_m40c.db'
Loading db file '/home/user/EDA_tools/synopsys/DC2005/X-2005.09-SP2/libraries/syn/gtech.db'
Loading db file '/home/user/EDA_tools/synopsys/DC2005/X-2005.09-SP2/libraries/syn/standard.sldb'
Loading link library 'ss_1v62_125c'
Loading link library 'tt_1v8_25c'
Loading link library 'ff_1v98_m40c'
Loading link library 'gtech'
Loading verilog file '/home/user/Desktop/slavecode.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/user/Desktop/slavecode.v
Warning: /home/user/Desktop/slavecode.v:53: 'count' is being read, but does not appear in the sensitivity
list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:55: 'sclbufferi' is being read, but does not appear in the
sensitivity list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:111: 'state' is being read, but does not appear in the sensitivity
list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:127: 'next' is being read, but does not appear in the sensitivity
list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:183: 'databuffer[7:1]' is being read, but does not appear in the
sensitivity list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:183: 'address' is being read, but does not appear in the
sensitivity list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:175: Potential simulation-synthesis mismatch if index exceeds size
of array '_nba_databuffer'. (ELAB-349)
Warning: /home/user/Desktop/slavecode.v:175: 'sdabufferi' is being read, but does not appear in the
sensitivity list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:175: Potential simulation-synthesis mismatch if index exceeds size
of array '_nba_flag_databuffer'. (ELAB-349)
Warning: /home/user/Desktop/slavecode.v:185: 'databuffer[0]' is being read, but does not appear in the
sensitivity list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:188: 'ackkey' is being read, but does not appear in the sensitivity
list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:230: Potential simulation-synthesis mismatch if index exceeds size
of array '_nba_databuffer'. (ELAB-349)
Warning: /home/user/Desktop/slavecode.v:230: Potential simulation-synthesis mismatch if index exceeds size
of array '_nba_flag_databuffer'. (ELAB-349)
Warning: /home/user/Desktop/slavecode.v:247: 'memaddress' is being read, but does not appear in the
sensitivity list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:265: 'rwbit' is being read, but does not appear in the sensitivity
list of the block. (ELAB-292)
Warning: /home/user/Desktop/slavecode.v:283: Potential simulation-synthesis mismatch if index exceeds size
of array '_nba_databuffer'. (ELAB-349)
Warning: /home/user/Desktop/slavecode.v:283: Potential simulation-synthesis mismatch if index exceeds size
of array '_nba_flag_databuffer'. (ELAB-349)
Warning: /home/user/Desktop/slavecode.v:340: 'notack' is being read, but does not appear in the sensitivity
list of the block. (ELAB-292)
Statistics for case statements in always block at line 142 in file
'/home/user/Desktop/slavecode.v'
===============================================
| Line | full/ parallel |
===============================================
| 153 | auto/auto |
===============================================
Warning: /home/user/Desktop/slavecode.v:327: Potential simulation-synthesis mismatch if index exceeds size
of array 'databuffer'. (ELAB-349)
Inferred memory devices in process
in routine slavecode line 95 in file
'/home/user/Desktop/slavecode.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| ackkey_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
===============================================================================
Inferred memory devices in process
in routine slavecode line 142 in file
'/home/user/Desktop/slavecode.v'.
===========================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===========================================================================
| notack_reg | Latch | 1 | N | N | N | N | - | - | - |
| rwbit_reg | Latch | 1 | N | N | N | N | - | - | - |
| databuffer_reg | Latch | 8 | N | N | N | N | - | - | - |
| memaddress_reg | Latch | 3 | N | N | N | N | - | - | - |
| sdabuffero_reg | Latch | 1 | N | N | N | N | - | - | - |
| memory_reg | Latch | 64 | N | N | N | N | - | - | - |
| count_reg | Latch | 4 | N | N | N | N | - | - | - |
| state_reg | Latch | 3 | N | N | N | N | - | - | - |
| address_reg | Latch | 7 | Y | N | N | N | - | - | - |
===========================================================================
Statistics for MUX_OPs
===========================================================
| block name/line | Inputs | Outputs | # sel inputs | MB |
===========================================================
| slavecode/247 | 8 | 8 | 3 | N |
| slavecode/327 | 8 | 1 | 3 | N |
===========================================================
Presto compilation completed successfully.
Current design is now '/home/user/Desktop/slavecode.db:slavecode'
Loaded 1 design.
Current design is 'slavecode'.
slavecode
design_vision-xg-t> #STEP3 set current design level #
current_design slavecode
link
uniquify
Current design is 'slavecode'.
Linking design 'slavecode'
Using the following designs and libraries:
--------------------------------------------------------------------------
slavecode /home/user/Desktop/slavecode.db
ss_1v62_125c (library) /home/user/lib/aci/sc-x/synopsys/ss_1v62_125c.db
tt_1v8_25c (library) /home/user/lib/aci/sc-x/synopsys/tt_1v8_25c.db
ff_1v98_m40c (library) /home/user/lib/aci/sc-x/synopsys/ff_1v98_m40c.db
1
design_vision-xg-t> #STEP4 define operations contidions #
#set_operating_conditions -library ss_1v62_125c
set_operating_conditions -library ss_1v62_125c
#set_wire_load_model -name csm18ull -library ss_lv62_125c
#set_wire_load_mode top
Removing min operating conditions from design 'slavecode'
Removing max operating conditions from design 'slavecode'
1
design_vision-xg-t> #STEP5 set the area constraints #
set_max_area 0
1
design_vision-xg-t> #STEP6 constraint IO and external environment#
#set_drive 0 [list reset]
#set_driving_cell -lib_cell PISUW -pin C [get_ports sclbufferi]
#set_driving_cell -lib_cell PBSU2W -pin C [get_ports sdabufferi]
#set_load 10 [all_outputs]
#set_max_fanout 10 slavecode
design_vision-xg-t> #STEP7 constraint timing #
create_clock -name "clock" -period 300 -waveform {0 150} { sclbufferi }
set_fix_hold clock
set_input_delay 5 -clock clock [all_inputs]
set_output_delay 0 -clock clock [all_outputs]
set_output_delay 0 -clock clock [get_ports {sdabuffero}]
set_clock_latency 5 clock
set_clock_uncertainty -setup 3 clock
set_clock_transition 0.2 [get_clocks clock]
create_clock -name "sda_bufferi" -period 300 -waveform {75 225} { sdabufferi }
set_clock_latency 5 sda_bufferi
set_clock_uncertainty -setup 3 sda_bufferi
set_clock_transition 0.2 [get_clocks sda_bufferi]
set_fix_hold sda_bufferi
set_input_delay 5 -clock sda_bufferi [all_inputs]
set_output_delay 0 -clock sda_bufferi [all_outputs]
set_output_delay 0 -clock sda_bufferi [get_ports {sdabuffero}]
1
design_vision-xg-t> #STEP8 set timing exceptions #
set_dont_touch_network [list sclbufferi ]
set_false_path -from [get_clocks clock] -to [get_clocks sda_bufferi]
set_false_path -from [get_clocks sda_bufferi] -to [get_clocks clock]
#set_min_delay 300 -from sdabuffero_reg -to [get_ports sdabuffero]
1
design_vision-xg-t> #STEP9 do the compile #
#compile_ultra
#compile -map_effort high -area_effort low -incremental_mapping
check_design
Warning: In design 'slavecode', cell 'C2516' does not drive any nets. (LINT-1)
Warning: In design 'slavecode', cell 'C2521' does not drive any nets. (LINT-1)
Warning: In design 'slavecode', cell 'C2527' does not drive any nets. (LINT-1)
Warning: In design 'slavecode', cell 'C2529' does not drive any nets. (LINT-1)
Warning: In design 'slavecode', cell 'C2539' does not drive any nets. (LINT-1)
Warning: In design 'slavecode', cell 'C2540' does not drive any nets. (LINT-1)
Warning: In design 'slavecode', cell 'C2542' does not drive any nets. (LINT-1)
1
design_vision-xg-t> report_timing
Information: Updating design information... (UID-85)
Warning: Design 'slavecode' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay
calculations involving these nets. (TIM-134)
Warning: Clock port 'clock' cannot be assigned input delay relative to clock 'sda_bufferi'. Ignoring the
value. (TIM-111)
Warning: Clock port 'clock' cannot be assigned input delay relative to clock 'sda_bufferi'. Ignoring the
value. (TIM-111)
Information: Timing loop detected. (OPT-150)
B_8/A B_8/Z C2353/CONTROL1_0 C2353/Z_3 C2393/DATA2_3 C2393/Z_3 C2404/DATA2_3 C2404/Z_3 count_reg
[3]/enable count_reg[3]/Q I_1/A I_1/Z
Information: Timing loop detected. (OPT-150)
C2352/CONTROL2_0 C2352/Z_7 C2400/DATA2_7 C2400/Z_7 C2413/DATA2_7 C2413/Z_7 databuffer_reg[7]/enable
databuffer_reg[7]/Q C2505/A C2505/Z C164/u76 C164/z1525 I_86/A I_86/Z C2544/A C2544/Z C1616/A C1616/Z B_10/A
B_10/Z
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'count_reg[3]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'databuffer_reg[7]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'count_reg[2]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'DATA4_1' and 'Z_1' on cell 'C2345'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'count_reg[1]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'count_reg[0]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'notack_reg'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'state_reg[2]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'state_reg[1]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'state_reg[0]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'DATA3_1' and 'Z_1' on cell 'C2346'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'DATA4_0' and 'Z_0' on cell 'C2345'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'DATA3_0' and 'Z_0' on cell 'C2346'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'databuffer_reg[6]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'databuffer_reg[5]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'databuffer_reg[4]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'databuffer_reg[3]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'databuffer_reg[2]'
to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'enable' and 'Q' on cell 'databuffer_reg[1]'
to break a timing loop. (OPT-314)
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : slavecode
Version: X-2005.09-SP2
Date : Fri Apr 2 16:24:03 2010
****************************************
# A fanout number of 1000 was used for high fanout net computations.
Operating Conditions: ss_1v62_125c Library: ss_1v62_125c
Wire Load Model Mode: top
Startpoint: ackkey_reg (rising edge-triggered flip-flop clocked by clock')
Endpoint: ackkey_reg (rising edge-triggered flip-flop clocked by clock')
Path Group: clock
Path Type: max
Point Incr Path
-----------------------------------------------------------
clock clock' (rise edge) 150.00 150.00
clock network delay (ideal) 5.00 155.00
ackkey_reg/clocked_on (**SEQGEN**) 0.00 155.00 r
ackkey_reg/Q (**SEQGEN**) 0.00 155.00 f
I_2/Z (GTECH_NOT) 0.00 155.00 r
C2344/Z_0 (*SELECT_OP_2.1_2.1_1) 0.00 155.00 r
ackkey_reg/next_state (**SEQGEN**) 0.00 155.00 r
data arrival time 155.00
clock clock' (rise edge) 450.00 450.00
clock network delay (ideal) 5.00 455.00
clock uncertainty -3.00 452.00
ackkey_reg/clocked_on (**SEQGEN**) 0.00 452.00 r
library setup time 0.00 452.00
data required time 452.00
-----------------------------------------------------------
data required time 452.00
data arrival time -155.00
-----------------------------------------------------------
slack (MET) 297.00
Startpoint: count_reg[0]
(positive level-sensitive latch clocked by sda_bufferi)
Endpoint: count_reg[0]
(positive level-sensitive latch clocked by sda_bufferi)
Path Group: sda_bufferi
Path Type: max
Point Incr Path
--------------------------------------------------------------------------
clock sda_bufferi (rise edge) 75.00 75.00
clock network delay (ideal) 5.00 80.00
time given to startpoint 5.00 85.00
count_reg[0]/data_in (**SEQGEN**) 0.00 85.00 f
count_reg[0]/Q (**SEQGEN**) 0.00 85.00 f
add_230/A_0 (*ADD_UNS_OP_4_1_4) 0.00 85.00 f
add_230/*cell*13/A[0] (DW01_inc_4) 0.00 85.00 f
add_230/*cell*13/U0/Z (GTECH_NOT) 0.00 85.00 r
add_230/*cell*13/SUM[0] (DW01_inc_4) 0.00 85.00 r
add_230/Z_0 (*ADD_UNS_OP_4_1_4) 0.00 85.00 r
C2394/Z_0 (*SELECT_OP_5.4_5.1_4) 0.00 85.00 r
C2405/Z_0 (*SELECT_OP_2.4_2.1_4) 0.00 85.00 r
count_reg[0]/data_in (**SEQGEN**) 0.00 85.00 r
data arrival time 85.00
clock sda_bufferi (rise edge) 75.00 75.00
clock network delay (ideal) 5.00 80.00
count_reg[0]/enable (**SEQGEN**) 0.00 80.00 r
time borrowed from endpoint 5.00 85.00
data required time 85.00
--------------------------------------------------------------------------
data required time 85.00
data arrival time -85.00
--------------------------------------------------------------------------
slack (MET) 0.00
Time Borrowing Information
--------------------------------------------------------------
sda_bufferi pulse width 150.00
library setup time 0.00
clock uncertainty -3.00
--------------------------------------------------------------
max time borrow 147.00
actual time borrow 5.00
--------------------------------------------------------------
1
最好能把你的问题总结一下，这么长！很难分析！
确实没怎么看明白，只把命令写出来啊
太多了，不容易看
不是吧，这么多都贴出来
感觉小编还没怎么入门啊……建议把dc的user guide好好看看吧。
加约束一般都是把约束语句写在一起，做成一个.tcl文件，然后依次运行的。
还有你的代码估计也有问题。在一个always模块里赋值符号右侧出现的变量最好都加到敏感列表里，这是写verilog代码的一种惯例了。
这个确实挺长的，最好总结一下
你把这么多的warning发出来，谁知道你想问什么啊。你要知道是哪里的约束出了问题，然后发出来啊
整理一下吧
Warning: /home/user/Desktop/slavecode.v:55: 'sclbufferi' is being read, but does not appear in the sensitivity list of the block. (ELAB-292)
这个是由于你的敏感列表中未添加这个信号，最好是用always @(*)包含所有的信号
Warning: /home/user/Desktop/slavecode.v:175: Potential simulation-synthesis mismatch if index exceeds size of array '_nba_databuffer'. (ELAB-349)
这个是由于数组的下标用变量来实现，不知道这个警告可以忽略不?
你的代码明显有问题。你取quartussII去查查代码
你的寄存器全部写成Latch了，先修改好RTL吧，路还很长。
感觉小编还没怎么入门啊……建议把dc的user guide好好看看吧。
加约束一般都是把约束语句写在一起，做成一个.tcl文件，然后依次运行的。
顶贴赚积分
顶贴赚积分
顶一下！