Vivado 2015.1 MIG生成DDR4控制器例化问题求助！（急）

Vivado 2015.1 MIG生成DDR4控制器例化一个ila,然后报错：WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xcvu095_0 and the probes file debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).

建议转linux去，实践证明在win下搞开发会让工作越来越糟糕，
Win快快死去

那是因为DDR中RAM需要的bmm elf文件没有吃进去，你可以参考example_top implement之后的impl_1目录下的脚本example_top.tcl.例如：

add_files -quiet /vivado_prj/ddr3_0_example.srcs/sources_1/ip/ddr3_0/ddr3_0.dcp

set_property netlist_only true [get_files /vivado_prj/ddr3_0_example.srcs/sources_1/ip/ddr3_0/ddr3_0.dcp]

add_files -quiet / vivado_prj/ddr3_0_example.runs/ila_ddrx_synth_1/ila_ddrx.dcp

add_files / vivado_prj/ ddr3_0_example.srcs/sources_1/ip/ddr3_0/sw/microblaze_mcs_ddr.bmm

set_property SCOPED_TO_REF ddr3_0 [get_files -all / vivado_prj/ ddr3_0_example.srcs/sources_1/ip/ddr3_0/sw/microblaze_mcs_ddr.bmm]

set_property SCOPED_TO_CELLS inst/u_ddr3_mem_intfc/u_ddr_cal_riu/mcs0[get_files -all / vivado_prj/ ddr3_0_example.srcs/sources_1/ip/ddr3_0/sw/microblaze_mcs_ddr.bmm]

add_files / vivado_prj/ ddr3_0_example.srcs/sources_1/ip/ddr3_0/sw/calibration_0/Debug/calibration_ddr.elf

set_property SCOPED_TO_REF ddr3_0 [get_files -all / vivado_prj/ ddr3_0_example.srcs/sources_1/ip/ddr3_0/sw/calibration_0/Debug/calibration_ddr.elf]

set_property SCOPED_TO_CELLSinst/u_ddr3_mem_intfc/u_ddr_cal_riu/mcs0/microblaze_I [get_files -all / vivado_prj/ddr3_0_example.srcs/sources_1/ip/ddr3_0/sw/calibration_0/Debug/calibration_ddr.elf]

也可以在官网搜有相关解答：
AR# 64923 MIG UltraScale - Hardware Manager Xicom error messages occuring after programming device
http://www.xilinx.com/support/answers/64923.html
Solution

Vivado 2015.1 and 2015.2

This issue can occur when using a MIG *.dcp instead of the *.xci as a result of the *.elf and *.bmm file association occurring incorrectly.

To resolve the issue, add the following commands to your scripts or project flow to properly associate the files to your design:

2015.1:

Elf Association

add_files /<location of *.elf file>/calibration_ddr.elf
set_property SCOPED_TO_REF <mig_inst_name> [get_files /<location of *.elf file>/calibration_ddr.elf]
set_property SCOPED_TO_CELLS inst/u_ddr_mc_cal/u_ddr_cal/mcs0/microblaze_I [get_files /<location of *.elf file>/calibration_ddr.elf]

BMM Association

add_files /<location of *.bmm file>/microblaze_mcs_ddr.bmm
set_property SCOPED_TO_REF <mig_inst_name> [get_files /<location of *.elf file>/microblaze_mcs_ddr.bmm]
set_property SCOPED_TO_CELLS inst/u_ddr_mc_cal/u_ddr_cal/mcs0 [get_files /<location of *.elf file>/microblaze_mcs_ddr.bmm]

2015.2:

ELF Association

add_files /<location of *.elf file>/calibration_ddr.elf
set_property SCOPED_TO_REF <mig_inst_name> [get_files *.elf]
set_property SCOPED_TO_CELLS {inst/u_ddr_cal_riu/mcs0/microblaze_I} [get_files /<location of *.elf file>/calibration_ddr.elf]

BMM Association

add_files /<location of *.elf file>/microblaze_mcs_ddr.bmm
set_property SCOPED_TO_REF <mig_inst_name> [get_files /<location of *.elf file>/microblaze_mcs_ddr.bmm]
set_property SCOPED_TO_CELLS {inst/u_ddr_cal_riu/mcs0/} [get_files /<location of *.elf file>/microblaze_mcs_ddr.bmm]

Vivado 2015.3 or Later:

This issue has additionally been seen in later versions of Vivado when .elf and .bmm files are not properly built into the design due to improper usage of the memory IP or the IP output files not being generated.

To verify if the memory IP elf and .bmm files are associated properly, the Vivado log file should have an info message similar to the following.  

This message can also be seen when running refresh_design from the Tcl prompt.

INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: ../mig_0_example.srcs/sources_1/ip/mig_0/sw/calibration_0/Debug/calibration_ddr.elf

If this message is not present, the .elf and .bmm files were not associated properly and the following message will occur within Hardware Manager:

WARNING: [Xicom 50-46] One or more detected MIG version registers have empty values: MIG properties will not be built.
Parameter Map Version: 1, Error Map Version: 0, Calibration Map Version: 0, Warning Map Version: 0
Invalid calibration version register value detected from MIG core: 000

The .elf and .bmm files are located in the following directories of the generated Memory IP core:

• core_name.srcs\sources_1\ip\ddr4_32_bit\sw\microblaze_mcs_ddr.bmm
• core_name.srcs\sources_1\ip\ddr4_32_bit\sw\calibration_0\Debug\calibration_ddr.elf

The files can be added to the project and properly associated with Tcl commands similar to the following:

add_files /<location of *.elf file>/calibration_ddr.elf
add_files /<location of *.bmm file>/microblaze_mcs_ddr.bmm
set_property SCOPED_TO_REF core_name_ddr4_mem_intfc [get_files *.elf]
set_property SCOPED_TO_CELLS u_ddr_cal_riu/mcs0/microblaze_I [get_files *.elf]
set_property SCOPED_TO_REF core_name_ddr4_mem_intfc [get_files *.bmm]
set_property SCOPED_TO_CELLS u_ddr_cal_riu/mcs0 [get_files *.bmm]

If using a Tcl script to build the design, ensure that both read_ip and generate_target commands are used for the Memory IP.

If using Synplify Pro, please reference (Xilinx Answer 65950).

Revision History:

   Thanks.