关于quartus宏功能管理向导配置的RAM在modelsim仿真时出现的问题

用quartusII 的宏功能管理向导配置了一个可同时读写的简单双口的RAM，实际需要48个单元，引了6根地址线，每个单元位宽为24，源程序中进行了例化赋初值，在modelsim中编写了testbench程序，但是仿真出来出现# Warning : Address pointed at port B is out of bound！# Time: 1381450000  Instance: vvram_control_tb.DUT.vvram_inst5.altsyncram_component
不是自己生成的RAM的Verilog程序吗?为什么会出错呢?
生成的RAM的程序为：
module vvram (
  rdclock,
  wrclock,
  rdaddress,
  wraddress,
  wren,
data,
   q);

input
[23:0]  data;
input
[5:0]  rdaddress;
input
  rdclock;
input
[5:0]  wraddress;
input
  wrclock;
input
  wren;
output
[23:0]  q;
parameter initial_file="vvram0.mif"; //change
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1
  wrclock;
tri0
  wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];

altsyncram
altsyncram_component (
.address_a (wraddress),
.clock0 (wrclock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.clock1 (rdclock),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
//altsyncram_component.init_file = "../../../vvram0.mif",
altsyncram_component.init_file = initial_file,  //change
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 48,
altsyncram_component.numwords_b = 48,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;

endmodule

我也遇见诸如此类的问题，显示Warning : Address pointed at port A is out of bound！
# Time: 10611000  Instance: test_ctrl.uint.out_ram.altsyncram_component；请问你是怎样解决的的?