求教：Module isn't defined and Vopt Compilier exiting
时间：10-02
整理：3721RD
点击：
小妹首次在贵论坛发贴，如有不合规范与要求处，敬请见谅：
问题现状：
想利用Modelsim SE PLUS 6.3a仿真带有UART内核（利用SOPC Builder工具生成）的Quartus II工程delay_core，在load design时出下述错误：
vsim work.delay_core
# vsim work.delay_core
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: [1] D:/delay_core_post_paper_answer/DelayCoreSimu/delay_core.vhd(80): (vopt-3473) Component instance "u1 : clock_multi" is not bound.
# ** Error: D:/delay_core_post_paper_answer/DelayCoreSimu/delay_cpu.v(3874): Module 'uart' is not defined.
# ** Error: D:/delay_core_post_paper_answer/data_latch.vhd(15): Vopt Compiler exiting
# Error loading design
小妹是Modelsim新手，对上述问题丈二和尚摸不着头脑，恳请高手不吝赐教！为了理清我、你、他及大家思路，下面稍微描述一下设计背景：
问题提出：
由于我对UART内核/Nios II处理系统不熟，不清楚DE2开发板对设计成品系统到底有多大实际的参考价值与移植效用，所以退而求其次，尝试利用Quartus II v7.1sp1+一些辅助工具（诸如Modelsim SE 6.3a、NIOS II 7.1 IDE、Precision Synthesis 2006a1.18及UCLinux_dist_20070130.tar，说来惭愧，到现在都没搞清，到底是否有必要使用上述软件或者欠缺会有啥负面影响，哪位高手能够在此“醍醐灌顶”一下，小妹不甚感激），选中Quartus II->Assignments->Settings->Analysis&Synthesis Settings->More Settings->Igore translate_off and Synthesis_off（off（default value）->on）运行全编译，按着编译报告“酌情”瞎改，费了好大劲，才改成如下规模：
1、 若想与data_latch数据锁存模块相连的SOPC输出的24位数据总线不为0，则目标芯片至少选为Cyclone II系列的EP2C8T144C8；
2、 如果目标芯片不变（可能用到JTAG调试模式，外时钟频率最好选为≥20MHz），还用原来的EP2C5T144C8（我手上也只有该款芯片及原来用AD6.6极限自动布线的见不得光的“万能板”(美其名曰万能板，实为“除了能做实验外，啥也不能干的实验万能开发板”)，当下SOPC输出的24位数据总线的高7位为0，问题出现的原因不清
我的想法：
由于SOPC输出的24位数据总线传输的是后续延时模块的延时预设值，现在延时值都不清，后面的设计根本没法验证；又由于调用人家（应该是Modelsim）可以综合的仿真库/标准库，在源程序还没搞懂的基础上，我酌情瞎改了一些，根本就不能保证程序的正确性，现在已经是高危操作了，打算通过2种途径（鄙人觉得风险相对较小）验证24位数据总线上的数据状态：一就是Modelsim，出现贴首的问题；二就是JTAG+Signal Tap II，结果Quartus II编译都过不去：
错误描述如下：
Error: Node instance "\non_zero_sample_depth_gen:segment_addr_counter" instantiated with unknown parameter "CARRY_CNT_EN"
Error: Can't elaborate inferred hierarchy "auto_signaltap_0|sld_signaltap_body|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter"
双击之，出现：“Can’t open encrypted file”C:/altera/71sp1/quartus/libraries/megafunctions/sld_ela_control.vhd”-license file support for this file includes compilation support,but doesn’t include viewing support.”的对话框，意即源码加密，打不开也定位不了。
预定位问题：
我把SOPC Builder生成的组成SOPC的所有模块的.v文件都拷贝到LPM库集合220model.v中，其中uart模块在module uart_rx_stimulus_source_character_source_rom_module子模块中做了如下修改（红字标出，还不知道改对了否），估计是此段修改与默认的uart模块描述相冲突，估计要在顶层文件中重新定义，但我把它原文拷入delay_cpu的顶层文件中，Modelsim SE PLUS 6.3a load design时依然出现贴首问题，下一步可能要费点劲了，再一次恳请高手不吝赐教下一步到底如何操作，小妹感激不尽：
module uart_rx_stimulus_source_character_source_rom_module (
// inputs:
clk,
incr_addr,
reset_n,
// sync_rxd,
// outputs:
new_rom,
ql,
safe,
// tx_data,
rx_data,
rxdata,
read_data
)
;
parameter POLL_RATE = 100;
output new_rom;
output [ 7: 0] ql;
//output [7 :0] tx_data;
output [7 :0] rx_data;
output [7 :0] rxdata;
output [15 :0] read_data;
reg [15 :0] readdata;
output safe;
input clk;
input incr_addr;
input reset_n;
//input sync_rxd;
reg [ 10: 0] address;
reg [ 10: 0] a;
reg d1_pre;
reg d2_pre;
reg d3_pre;
reg d4_pre;
reg d5_pre;
reg d6_pre;
reg d7_pre;
reg d8_pre;
reg d9_pre;
reg [ 7: 0] mem_array [1023: 0];
reg [ 31: 0] mutex [ 1: 0];
reg new_rom;
reg pre;
//reg [ 7: 0] qe;
wire safe;
//reg [5:0] div;
// reg dc;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
…….
reg safe_delay;
reg [31:0] poll_count;
reg [31:0] mutex_handle;
wire interactive = 1'b1 ;
assign safe = (address < mutex[1]);
//assign safe = (address < mutex[0]);
initial poll_count = POLL_RATE;
always @(posedge clk or negedge reset_n) begin
if (reset_n ！== 1) begin
safe_delay <= 0;
end else begin
safe_delay <= safe;
end
end // safe_delay
always @(posedge clk or negedge reset_n) begin
if (reset_n ！== 1) begin // dont worry about null _stream.dat file
// address <= 0;
// mem_array[0] <= 0;
mutex[0] <= 0;
mutex[1] <= 0;
pre <= 0;
end else begin // deal with the non-reset case
pre <= 0;
// if (incr_addr && safe) address <= address + 1;
if (mutex[0] && ！safe && safe_delay) begin
// and blast the mutex after falling edge of safe if interactive
if (interactive) begin
// mutex_handle = $fopen ("D:/delay_core_post_paper_answer/delay_cpu_sim/uart_input_data_mutex.dat");
$fdisplay (mutex_handle, "0");
$fclose (mutex_handle);
// $display ($stime, "\t%m:\n\t\tMutex cleared！");
end else begin
// sleep until next reset, do not bash mutex.
wait (！reset_n);
end
end
end
//if (reset_n==1)
$readmemh("D:/delay_core_post_paper_answer/delay_cpu_sim/uart_input_data_stream.dat", mem_array);
//else
// mem_array<=0;
end
//end // OK to bash mutex.
/*if (poll_count < POLL_RATE) begin // wait
poll_count = poll_count + 1;
end else begin // do the interesting stuff.
poll_count = 0;
$readmemh ("D:/delay_core_post_paper_answer/delay_cpu_sim/uart_input_data_mutex.dat", mutex);
if (mutex[0] && ！safe) begin
// read stream into mem_array after current characters are gone！
// save mutex[0] value to compare to address (generates 'safe')
mutex[1] <= mutex[0];
// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
$readmemh("D:/delay_core_post_paper_answer/delay_cpu_sim/uart_input_data_stream.dat", mem_array);
// bash address and send pulse outside to send the char:
address <= 0;
pre <= -1;
end // else mutex miss...
end // poll_count
end // reset
end // posedge clk
*/
always @(mem_array[address] or reset_n or address or a) begin
if (reset_n==1)
begin
if (mem_array[address]==0)
a <=address;
end
else
a<=0;
if (reset_n==1)
begin
if (address <=a)
begin
if (mem_array[address]<=39 && mem_array[address]>=30)
begin
readdata[3: 0]<=mem_array[address]-30;
address<=address+1;
end
else if (mem_array[address]<=46 && mem_array[address]>=41)
begin
readdata[3: 0]<=mem_array[address]-31;
address<=address+1;
end
if (mem_array[address]<=39 && mem_array[address]>=30)
begin
readdata[7: 4]<=mem_array[address]-30;
address<=address+1;
end
else if (mem_array[address]<=46 && mem_array[address]>=41)
begin
readdata[7: 4]<=mem_array[address]-31;
address<=address+1;
end
if (mem_array[address]<=39 && mem_array[address]>=30)
begin
readdata[11: 8]<=mem_array[address]-30;
address<=address+1;
end
else if (mem_array[address]<=46 && mem_array[address]>=41)
begin
readdata[11: 8]<=mem_array[address]-31;
address<=address+1;
end
if (mem_array[address]<=39 && mem_array[address]>=30)
begin
readdata[15: 12]<=mem_array[address]-30;
address<=address+1;
end
else if (mem_array[address]<=46 && mem_array[address]>=41)
begin
readdata[15: 12]<=mem_array[address]-31;
address<=address+1;
end
end
end
else
readdata<=0;
end
assign rxdata=mem_array[address];
assign read_data=readdata;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
问题现状：
想利用Modelsim SE PLUS 6.3a仿真带有UART内核（利用SOPC Builder工具生成）的Quartus II工程delay_core，在load design时出下述错误：
vsim work.delay_core
# vsim work.delay_core
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: [1] D:/delay_core_post_paper_answer/DelayCoreSimu/delay_core.vhd(80): (vopt-3473) Component instance "u1 : clock_multi" is not bound.
# ** Error: D:/delay_core_post_paper_answer/DelayCoreSimu/delay_cpu.v(3874): Module 'uart' is not defined.
# ** Error: D:/delay_core_post_paper_answer/data_latch.vhd(15): Vopt Compiler exiting
# Error loading design
小妹是Modelsim新手，对上述问题丈二和尚摸不着头脑，恳请高手不吝赐教！为了理清我、你、他及大家思路，下面稍微描述一下设计背景：
问题提出：
由于我对UART内核/Nios II处理系统不熟，不清楚DE2开发板对设计成品系统到底有多大实际的参考价值与移植效用，所以退而求其次，尝试利用Quartus II v7.1sp1+一些辅助工具（诸如Modelsim SE 6.3a、NIOS II 7.1 IDE、Precision Synthesis 2006a1.18及UCLinux_dist_20070130.tar，说来惭愧，到现在都没搞清，到底是否有必要使用上述软件或者欠缺会有啥负面影响，哪位高手能够在此“醍醐灌顶”一下，小妹不甚感激），选中Quartus II->Assignments->Settings->Analysis&Synthesis Settings->More Settings->Igore translate_off and Synthesis_off（off（default value）->on）运行全编译，按着编译报告“酌情”瞎改，费了好大劲，才改成如下规模：
1、 若想与data_latch数据锁存模块相连的SOPC输出的24位数据总线不为0，则目标芯片至少选为Cyclone II系列的EP2C8T144C8；
2、 如果目标芯片不变（可能用到JTAG调试模式，外时钟频率最好选为≥20MHz），还用原来的EP2C5T144C8（我手上也只有该款芯片及原来用AD6.6极限自动布线的见不得光的“万能板”(美其名曰万能板，实为“除了能做实验外，啥也不能干的实验万能开发板”)，当下SOPC输出的24位数据总线的高7位为0，问题出现的原因不清
我的想法：
由于SOPC输出的24位数据总线传输的是后续延时模块的延时预设值，现在延时值都不清，后面的设计根本没法验证；又由于调用人家（应该是Modelsim）可以综合的仿真库/标准库，在源程序还没搞懂的基础上，我酌情瞎改了一些，根本就不能保证程序的正确性，现在已经是高危操作了，打算通过2种途径（鄙人觉得风险相对较小）验证24位数据总线上的数据状态：一就是Modelsim，出现贴首的问题；二就是JTAG+Signal Tap II，结果Quartus II编译都过不去：
错误描述如下：
Error: Node instance "\non_zero_sample_depth_gen:segment_addr_counter" instantiated with unknown parameter "CARRY_CNT_EN"
Error: Can't elaborate inferred hierarchy "auto_signaltap_0|sld_signaltap_body|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter"
双击之，出现：“Can’t open encrypted file”C:/altera/71sp1/quartus/libraries/megafunctions/sld_ela_control.vhd”-license file support for this file includes compilation support,but doesn’t include viewing support.”的对话框，意即源码加密，打不开也定位不了。
预定位问题：
我把SOPC Builder生成的组成SOPC的所有模块的.v文件都拷贝到LPM库集合220model.v中，其中uart模块在module uart_rx_stimulus_source_character_source_rom_module子模块中做了如下修改（红字标出，还不知道改对了否），估计是此段修改与默认的uart模块描述相冲突，估计要在顶层文件中重新定义，但我把它原文拷入delay_cpu的顶层文件中，Modelsim SE PLUS 6.3a load design时依然出现贴首问题，下一步可能要费点劲了，再一次恳请高手不吝赐教下一步到底如何操作，小妹感激不尽：
module uart_rx_stimulus_source_character_source_rom_module (
// inputs:
clk,
incr_addr,
reset_n,
// sync_rxd,
// outputs:
new_rom,
ql,
safe,
// tx_data,
rx_data,
rxdata,
read_data
)
;
parameter POLL_RATE = 100;
output new_rom;
output [ 7: 0] ql;
//output [7 :0] tx_data;
output [7 :0] rx_data;
output [7 :0] rxdata;
output [15 :0] read_data;
reg [15 :0] readdata;
output safe;
input clk;
input incr_addr;
input reset_n;
//input sync_rxd;
reg [ 10: 0] address;
reg [ 10: 0] a;
reg d1_pre;
reg d2_pre;
reg d3_pre;
reg d4_pre;
reg d5_pre;
reg d6_pre;
reg d7_pre;
reg d8_pre;
reg d9_pre;
reg [ 7: 0] mem_array [1023: 0];
reg [ 31: 0] mutex [ 1: 0];
reg new_rom;
reg pre;
//reg [ 7: 0] qe;
wire safe;
//reg [5:0] div;
// reg dc;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
…….
reg safe_delay;
reg [31:0] poll_count;
reg [31:0] mutex_handle;
wire interactive = 1'b1 ;
assign safe = (address < mutex[1]);
//assign safe = (address < mutex[0]);
initial poll_count = POLL_RATE;
always @(posedge clk or negedge reset_n) begin
if (reset_n ！== 1) begin
safe_delay <= 0;
end else begin
safe_delay <= safe;
end
end // safe_delay
always @(posedge clk or negedge reset_n) begin
if (reset_n ！== 1) begin // dont worry about null _stream.dat file
// address <= 0;
// mem_array[0] <= 0;
mutex[0] <= 0;
mutex[1] <= 0;
pre <= 0;
end else begin // deal with the non-reset case
pre <= 0;
// if (incr_addr && safe) address <= address + 1;
if (mutex[0] && ！safe && safe_delay) begin
// and blast the mutex after falling edge of safe if interactive
if (interactive) begin
// mutex_handle = $fopen ("D:/delay_core_post_paper_answer/delay_cpu_sim/uart_input_data_mutex.dat");
$fdisplay (mutex_handle, "0");
$fclose (mutex_handle);
// $display ($stime, "\t%m:\n\t\tMutex cleared！");
end else begin
// sleep until next reset, do not bash mutex.
wait (！reset_n);
end
end
end
//if (reset_n==1)
$readmemh("D:/delay_core_post_paper_answer/delay_cpu_sim/uart_input_data_stream.dat", mem_array);
//else
// mem_array<=0;
end
//end // OK to bash mutex.
/*if (poll_count < POLL_RATE) begin // wait
poll_count = poll_count + 1;
end else begin // do the interesting stuff.
poll_count = 0;
$readmemh ("D:/delay_core_post_paper_answer/delay_cpu_sim/uart_input_data_mutex.dat", mutex);
if (mutex[0] && ！safe) begin
// read stream into mem_array after current characters are gone！
// save mutex[0] value to compare to address (generates 'safe')
mutex[1] <= mutex[0];
// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
$readmemh("D:/delay_core_post_paper_answer/delay_cpu_sim/uart_input_data_stream.dat", mem_array);
// bash address and send pulse outside to send the char:
address <= 0;
pre <= -1;
end // else mutex miss...
end // poll_count
end // reset
end // posedge clk
*/
always @(mem_array[address] or reset_n or address or a) begin
if (reset_n==1)
begin
if (mem_array[address]==0)
a <=address;
end
else
a<=0;
if (reset_n==1)
begin
if (address <=a)
begin
if (mem_array[address]<=39 && mem_array[address]>=30)
begin
readdata[3: 0]<=mem_array[address]-30;
address<=address+1;
end
else if (mem_array[address]<=46 && mem_array[address]>=41)
begin
readdata[3: 0]<=mem_array[address]-31;
address<=address+1;
end
if (mem_array[address]<=39 && mem_array[address]>=30)
begin
readdata[7: 4]<=mem_array[address]-30;
address<=address+1;
end
else if (mem_array[address]<=46 && mem_array[address]>=41)
begin
readdata[7: 4]<=mem_array[address]-31;
address<=address+1;
end
if (mem_array[address]<=39 && mem_array[address]>=30)
begin
readdata[11: 8]<=mem_array[address]-30;
address<=address+1;
end
else if (mem_array[address]<=46 && mem_array[address]>=41)
begin
readdata[11: 8]<=mem_array[address]-31;
address<=address+1;
end
if (mem_array[address]<=39 && mem_array[address]>=30)
begin
readdata[15: 12]<=mem_array[address]-30;
address<=address+1;
end
else if (mem_array[address]<=46 && mem_array[address]>=41)
begin
readdata[15: 12]<=mem_array[address]-31;
address<=address+1;
end
end
end
else
readdata<=0;
end
assign rxdata=mem_array[address];
assign read_data=readdata;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
uart内核（NIOS II处理系统）+JTAG调试如何具体操作
原来用10MHz外时钟时，SOPC始终加不进，换成20MHz时钟后，才勉强加进delay_cpu，而10MHz与20MHz的差别，就是前者不能使用JTAG调试模式，又加上** Warning: [1] D:/delay_core_post_paper_answer/DelayCoreSimu/delay_core.vhd(80): (vopt-3473) Component instance "u1 : clock_multi" is not bound.这一Modelsim警告，十有八九咱的设计已经挂钩了JTAG调试模式，调用jtag_uart模块，编译又过不去：
Error: Node instance "jtag_pli" instantiates undefined entity "jtag_pli"，挂钩加密源码C:/altera/71sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v
引出三大问题：
1、uart内核（NIOS II处理系统）+JTAG调试如何具体操作（依托 quartus II v7.1sp1）
2、jtag_uart咋用，能否与uart共存?
3、解密alt_jtag_atlantic.v源码谁有?恳请资源共享。
程序好长@
程序好长@
沙发..同求