请问我用的FPGA的时钟源和ODDR2的IP核可以用在cpld中吗？

时间：10-02 整理：3721RD 点击：

我在Xilinx ISE中直接把原来用于FPGA的程序改为CPLD的了，直接改到器件，综合会出现错误：ERROR:NgdBuild:604 - logical block 'oddr2_inst' with type 'ODDR2' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
case mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'ODDR2' is not supported in target 'xbr'.
ERROR:NgdBuild:973 - The IBUFG symbol 'clk_inst/clkin1_buf' is not supported in
the xbr architecture.
ERROR:NgdBuild:604 - logical block 'clk_inst/dcm_sp_inst' with type 'DCM_SP'
could not be resolved. A pin name misspelling can cause this, a missing edif
or ngc file, case mismatch between the block name and the edif or ngc file
name, or the misspelling of a type name. Symbol 'DCM_SP' is not supported in
target 'xbr'.
ERROR:NgdBuild:770 - IBUF 'clk_IBUF' and IBUFG 'clkin1_buf' on net 'clk_IBUF'
are lined up in series. Buffers of the same direction cannot be placed in
series.
ERROR:NgdBuild:925 - input net 'clk_IBUF' is connected to the incorrect side of
buffer(s):
ERROR:NgdBuild:770 - BUFG 'clkout1_buf' and BUFG 'clkout1_buf' on net
'clk_inst/clk0' are lined up in series. Buffers of the same direction cannot
be placed in series.
ERROR:NgdBuild:770 - BUFG 'clkout3_buf' and BUFG 'clkout3_buf' on net
'clk_inst/clk180' are lined up in series. Buffers of the same direction
cannot be placed in series.
ERROR:NgdBuild:770 - BUFG 'clkout4_buf' and BUFG 'clkout4_buf' on net
'clk_inst/clk270' are lined up in series. Buffers of the same direction
cannot be placed in series.
ERROR:NgdBuild:770 - BUFG 'clkout2_buf' and BUFG 'clkout2_buf' on net
'clk_inst/clk90' are lined up in series. Buffers of the same direction cannot
be placed in series.
有那位大神知道吗?

上一篇：Xilinx ISE 仿真出错“Non-net variable cannot be connected to inout port fdata”
下一篇：VIRTEX4_

FPGA ASIC quartus Xilinx vivado verilog ALTERA CPLD 集成电路相关文章：

栏目分类