32位流水线加法器verilog

/*32bit pipeline adder*/
`timescale 1ns / 1ps
module Pipel_ADD(clk,a,b,cin,cout,sum);
//I/O define
  input [31:0] a;
  input [31:0] b;
  input clk;
  input cin;
  output cout;
  output [31:0] sum;
//data type
  reg    [31:0] sum;
  reg  cout;
  reg [31:0] tempa,tempb;
  reg tempcin;
//First level
  reg [23:0] a1,b1;
  reg co1;
  reg [7:0] sum1;
//Second level
  reg [15:0] a2,b2;
  reg co2;
  reg [15:0] sum2;
//Third level
  reg [7:0] a3,b3;
  reg co3;
  reg [23:0] sum3;
/***********code*********/
always@(posedge clk)
  begin
   tempa<=a;
   tempb<=b;
   tempcin<=cin;
  end
//First
always@(posedge clk)  
  begin
   {co1,sum1}<=9'b0+tempa[7:0]+tempb[7:0]+tempcin;
           a1<=tempa[31:8];
   b1<=tempb[31:8];
  end
//Second
always@(posedge clk)
  begin
   {co2,sum2}<={9'b0+a1[7:0]+b1[7:0]+co1,sum1};
           a2<=a1[23:8];
     b2<=b1[23:8];
  end
//Third
always@(posedge clk)
  begin
   {co3,sum3}<={9'b0+a2[7:0]+b2[7:0]+co2,sum2};
           a3<=a2[15:8];
     b3<=b2[15:8];
  end
//Forth
always@(posedge clk)
  begin
   {cout,sum}<={9'b0+a3[7:0]+b3[7:0]+co3,sum3};
  end
endmodule