VHDL程序编译报错

--6进制计数器
--RTL方式描述
library ieee;
use ieee.std_logic_1164.all;
use work.new.all;
entity counter_6_spe is
port(clk,rs:in std_logic;
     q1,q2,q3ut std_logic);
end entity counter_6_spe;
architecture rtl of counter_6_spe is
component dff is
port (d,rs,clk:in std_logic;
             qut std_logic);
end component dff;
component djk is
port (j,k,rs,clk:in std_logic;
               qut std_logic);
end component djk;
component and2 is
port (a,b:in std_logic;
        c:out std_logic);
end component and2;
component nor2 is
port (a,b:in std_logic;
        c:out std_logic);
end component nor2;
signal jin,kin,q1_out,q2_out,q3_out:std_logic;
begin
u1:nor2
   port map(q3_out,q2_out,jin);
u2:and2
   port map(q3_out,q2_out,kin);
u3:djk
   port map(jin,kin,rs,clk,q1_out);
u4:dff
   port map(q1_out,rs,clk,q2_out);
u5:dff
   port map(q2_out,rs,clk,q3_out);
   q1<=q1_out;
q2<=q2_out;
q3<=q3_out;
end architecture rtl;
书上是上面那样写的，但编译报错：
Error (10500): VHDL syntax error at counter_6_spe.vhd(4) near text "new";  expecting an identifier ("new" is a reserved keyword), or a string literal, or "all", or a character

根据Error信息，应该是下面这句出错：
use work.new.all;
new是vHDL的保留关键字。去掉这句看看。

我用的是verilog

VHDL不怎么看的懂

谢谢啊。