微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 嵌入式设计讨论 > FPGA,CPLD和ASIC > ise 使用DCM问题:Block dclk/DCM_SP is not a recognized logical block

ise 使用DCM问题:Block dclk/DCM_SP is not a recognized logical block

时间:10-02 整理:3721RD 点击:

WARNING:MapLib:328 - Block dclk/DCM_SP is not a recognized logical block. The
   mapper will continue to process the design but there may be design problems
   if this block does not get trimmed.
用ise core generator 的Clocking Wizard 生成DCM,map时出现上述警告,请问是啥问题?

确认你在core generator生成DCM的时候选择的fpga期间类型跟你跑ISE的期间类型一致。
任何问题:log to www.xilinx.com, then search your problem: "MapLib:328"

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top