求解决dsp builder中signal compiler编译后的warming~

Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.   
Critical Warning (332169): From Clock (Rise) to Clock (Rise) (setup and hold)
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for detailsCritical
Warning (169085): No exact pin location assignment(s) for 50 pins of 50 total pins
Warning (10036): Verilog HDL or VHDL warning at alt_dspbuilder_altimult.vhd(80): object "enadff" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_dspbuilder_altimult.vhd(85): object "aclr_i" assigned a value but never read

这些warming怎么排除呢?请详细说明。谢谢