Quartus II中综合例化后无元件
下附为了体现调用模块部分而修改精简过的代码：
module cpu_test(Clock,nReset,sel8_1,sel8_2,sel3_1,sel4_1,sel2_1,sel2_2,wr_en,inc_SP,dec_SP,inc_pc,load_pc,R_in);
input Clock, nReset;
input [2:0] sel8_1, sel8_2;
input inc_SP, dec_SP,inc_pc,load_pc;
input wr_en;
input [1:0] sel3_1, sel4_1;
input sel2_1, sel2_2;
input [7:0] R_in;
//instruction
wire [3:0] opcode;
wire [2:0] Rd, Rs;
wire [8:0] imm_1; //MOVI RD,#IMM_1
wire [11:0] imm_2; //JUMP LABEL(OFFSET=#IMM_2)
//wire connection signals
wire [15:0] alu_out, oprand_1,oprand_2, RAM_addr, data_i, data_o;
wire [15:0] PC_offset, address, IR;
wire [15:0] pc_address;
wire [15:0] Reg_Bus, imm9_ext, imm12_ext;
wire [7:0] R_en;
wire [15:0] R0,R1,R2,R3,R4,R5,R6,R7;
mux8 mux8_1(R0,R1,R2,R3,R4,R5,R6,R7,sel8_1,oprand_1); //Rd
mux8 mux8_2(R0,R1,R2,R3,R4,R5,R6,R7,sel8_2,oprand_2); //Rs
mux3 mux3_1(oprand_1,alu_out,pc_address,sel3_1,data_i);
mux4 mux4_1(oprand_2,alu_out,imm9_ext,data_o,sel4_1,Reg_Bus);
mux2 mux2_1(oprand_2,R0,sel2_1,RAM_addr);
mux2 mux2_2(imm9_ext,imm12_ext,sel2_2,PC_offset);
ALU ALU_1(opcode,oprand_1,oprand_2,alu_out);
bit_ext bit_ext_1(imm_1,imm9_ext);
bit_ext #(12,16) bit_ext_2(imm_2,imm12_ext);
dec3to8 decoder_1(Rd,R_en);
regn R_0 (Reg_Bus,R_in[0],Clock,nReset,R0);
regn R_1 (Reg_Bus,R_in[1],Clock,nReset,R1);
regn R_2 (Reg_Bus,R_in[2],Clock,nReset,R2);
regn R_3 (Reg_Bus,R_in[3],Clock,nReset,R3);
regn R_4 (Reg_Bus,R_in[4],Clock,nReset,R4);
regn R_5 (Reg_Bus,R_in[5],Clock,nReset,R5);
regn R_6 (Reg_Bus,R_in[6],Clock,nReset,R6);
regn R_7 (Reg_Bus,R_in[7],Clock,nReset,R7);
pc pc_0 (Clock,nReset,PC_offset,inc_pc,load_pc,pc_address);
ROM ROM_0 (pc_address,IR);
assign opcode = IR[15:12];
assign Rd = IR[11:9];
assign Rs = IR[8:6];
assign imm_1 = IR[8:0];
assign imm_2 = IR [11:0];
RAM RAM_0 (data_i,RAM_addr,wr_en,data_o);
endmodule
建议
你看一下 寄存器使用个数是多少
如果也是0 的话就说明 你的程序有问题，根本没有有效输出
谢谢楼上的大哥的建议
我开始也认为是程序的问题，于是我把顶层模块中的逻辑和时序部分都删除了，只是简单的调用了底层的所有模块（如我如上附的程序）。除了Clock和nReset是原来系统的输入信号外，其他的输入信号都是给这些底层模块的控制信号，因为这些控制信号是顶层模块中的逻辑和时序部分给的所以现在也删除了，所以现在为了能综合，于是通过系统输入信号来给这些模块控制信号。但是现在程序虽然只是简单的把这些模块例化，综合后的系统还是零LE使用率，也就是没有实际综合成器件，所以我现在也措手无策了。
（所有底层模块都是可综合并且占用FPGA逻辑资源的）
方便的话，把QuartusII软件编译的信息贴出来来看看，特别是关于综合和适配时的编译报告；也可以只先综合一下看看结果以及报告。
这个是整个编译过程的信息：
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
Info: Processing started: Wed Oct 17 12:03:22 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu_top -c cpu_top
Info: Found 1 design units, including 1 entities, in source file cpu_test.v
Info: Found entity 1: cpu_test
Info: Found 1 design units, including 1 entities, in source file 7to16_ext.v
Info: Found entity 1: bit_ext
Info: Found 1 design units, including 1 entities, in source file ALU.v
Info: Found entity 1: ALU
Info: Found 1 design units, including 1 entities, in source file dec3to8.v
Info: Found entity 1: dec3to8
Info: Found 1 design units, including 1 entities, in source file mux2.v
Info: Found entity 1: mux2
Info: Found 1 design units, including 1 entities, in source file mux3.v
Info: Found entity 1: mux3
Info: Found 1 design units, including 1 entities, in source file mux4.v
Info: Found entity 1: mux4
Info: Found 1 design units, including 1 entities, in source file mux8.v
Info: Found entity 1: mux8
Info: Found 1 design units, including 1 entities, in source file Program_Counter.v
Info: Found entity 1: pc
Info: Found 1 design units, including 1 entities, in source file RAM.v
Info: Found entity 1: RAM
Info: Found 1 design units, including 1 entities, in source file regn.v
Info: Found entity 1: regn
Info: Found 1 design units, including 1 entities, in source file ROM.v
Info: Found entity 1: ROM
Info: Found 1 design units, including 1 entities, in source file SP_regn.v
Info: Found entity 1: SP_regn
Info: Elaborating entity "cpu_test" for the top level hierarchy
Info: Elaborating entity "mux8" for hierarchy "mux8:mux8_1"
Info: Elaborating entity "mux3" for hierarchy "mux3:mux3_1"
Info: Elaborating entity "mux4" for hierarchy "mux4:mux4_1"
Info: Elaborating entity "mux2" for hierarchy "mux2:mux2_1"
Info: Elaborating entity "ALU" for hierarchy "ALU:ALU_1"
Info: Elaborating entity "bit_ext" for hierarchy "bit_ext:bit_ext_1"
Info: Elaborating entity "bit_ext" for hierarchy "bit_ext:bit_ext_2"
Info: Elaborating entity "dec3to8" for hierarchy "dec3to8:decoder_1"
Info: Elaborating entity "regn" for hierarchy "regn:R_0"
Info: Elaborating entity "pc" for hierarchy "pc:pc_0"
Info (10264): Verilog HDL Case Statement information at Program_Counter.v(12): all case item expressions in this case statement are onehot
Info: Elaborating entity "ROM" for hierarchy "ROM:ROM_0"
Warning (10030): Net "memory.datain[15]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[14]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[13]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[12]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[11]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[10]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[9]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[8]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[7]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[6]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[5]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[4]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[3]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[2]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[1]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[0]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[5]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[4]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[3]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[2]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[1]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[0]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Info: Elaborating entity "RAM" for hierarchy "RAM:RAM_0"
Warning: Port "ordered port 0" on the entity instantiation of "ROM_0" is connected to a signal of width 1. The formal width of the signal in the module is 16. Extra bits will be driven by GND.
Warning: Port "ordered port 5" on the entity instantiation of "pc_0" is connected to a signal of width 1. The formal width of the signal in the module is 16. Extra bits will be left dangling without any fanout logic.
Warning: Port "ordered port 0" on the entity instantiation of "decoder_1" is connected to a signal of width 1. The formal width of the signal in the module is 3. Extra bits will be driven by GND.
Warning: Port "ordered port 2" on the entity instantiation of "mux3_1" is connected to a signal of width 1. The formal width of the signal in the module is 16. Extra bits will be driven by GND.
Info: Implemented 27 device resources after synthesis - the final resource count might be different
Info: Implemented 27 input pins
Info: Implemented 0 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 26 warnings
Info: Allocated 121 megabytes of memory during processing
Info: Processing ended: Wed Oct 17 12:03:23 2007
Info: Elapsed time: 00:00:01
Info: Generated suppressed messages file D:/My Project/16bitRISC/without_pipeline/cpu_top.map.smsg
Info: *******************************************************************
Info: Running Quartus II Partition Merge
Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
Info: Processing started: Wed Oct 17 12:03:24 2007
Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off cpu_top -c cpu_top --merge=on
Info: Using synthesis netlist for partition "Top"
Info: Netlist merging resolved 1 partition(s) out of the 1 partition(s) found
Warning: Design contains 27 input pin(s) that do not drive logic
Warning: No output dependent on input pin "Clock"
Warning: No output dependent on input pin "nReset"
Warning: No output dependent on input pin "sel8_1[0]"
Warning: No output dependent on input pin "sel8_1[1]"
Warning: No output dependent on input pin "sel8_1[2]"
Warning: No output dependent on input pin "sel8_2[0]"
Warning: No output dependent on input pin "sel8_2[1]"
Warning: No output dependent on input pin "sel8_2[2]"
Warning: No output dependent on input pin "sel3_1[0]"
Warning: No output dependent on input pin "sel3_1[1]"
Warning: No output dependent on input pin "sel4_1[0]"
Warning: No output dependent on input pin "sel4_1[1]"
Warning: No output dependent on input pin "sel2_1"
Warning: No output dependent on input pin "sel2_2"
Warning: No output dependent on input pin "wr_en"
Warning: No output dependent on input pin "inc_SP"
Warning: No output dependent on input pin "dec_SP"
Warning: No output dependent on input pin "inc_pc"
Warning: No output dependent on input pin "load_pc"
Warning: No output dependent on input pin "R_in[0]"
Warning: No output dependent on input pin "R_in[1]"
Warning: No output dependent on input pin "R_in[2]"
Warning: No output dependent on input pin "R_in[3]"
Warning: No output dependent on input pin "R_in[4]"
Warning: No output dependent on input pin "R_in[5]"
Warning: No output dependent on input pin "R_in[6]"
Warning: No output dependent on input pin "R_in[7]"
Info: Quartus II Partition Merge was successful. 0 errors, 28 warnings
Info: Allocated 97 megabytes of memory during processing
Info: Processing ended: Wed Oct 17 12:03:25 2007
Info: Elapsed time: 00:00:01
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
Info: Processing started: Wed Oct 17 12:03:26 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off cpu_top -c cpu_top
Info: Selected device EP2C20F484C7 for design "cpu_top"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
Info: Previous placement does not exist for 27 of 27 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP2C15AF484C7 is compatible
Info: Device EP2C35F484C7 is compatible
Info: Device EP2C50F484C7 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location C4
Info: Pin ~nCSO~ is reserved at location C3
Info: Pin ~LVDS91p/nCEO~ is reserved at location W20
Warning: No exact pin location assignment(s) for 27 pins of 27 total pins
Info: Pin Clock not assigned to an exact location on the device
Info: Pin nReset not assigned to an exact location on the device
Info: Pin sel8_1[0] not assigned to an exact location on the device
Info: Pin sel8_1[1] not assigned to an exact location on the device
Info: Pin sel8_1[2] not assigned to an exact location on the device
Info: Pin sel8_2[0] not assigned to an exact location on the device
Info: Pin sel8_2[1] not assigned to an exact location on the device
Info: Pin sel8_2[2] not assigned to an exact location on the device
Info: Pin sel3_1[0] not assigned to an exact location on the device
Info: Pin sel3_1[1] not assigned to an exact location on the device
Info: Pin sel4_1[0] not assigned to an exact location on the device
Info: Pin sel4_1[1] not assigned to an exact location on the device
Info: Pin sel2_1 not assigned to an exact location on the device
Info: Pin sel2_2 not assigned to an exact location on the device
Info: Pin wr_en not assigned to an exact location on the device
Info: Pin inc_SP not assigned to an exact location on the device
Info: Pin dec_SP not assigned to an exact location on the device
Info: Pin inc_pc not assigned to an exact location on the device
Info: Pin load_pc not assigned to an exact location on the device
Info: Pin R_in[0] not assigned to an exact location on the device
Info: Pin R_in[1] not assigned to an exact location on the device
Info: Pin R_in[2] not assigned to an exact location on the device
Info: Pin R_in[3] not assigned to an exact location on the device
Info: Pin R_in[4] not assigned to an exact location on the device
Info: Pin R_in[5] not assigned to an exact location on the device
Info: Pin R_in[6] not assigned to an exact location on the device
Info: Pin R_in[7] not assigned to an exact location on the device
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 27 (unused VREF, 3.30 VCCIO, 27 input, 0 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 41 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used -- 31 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 43 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 40 pins available
Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 39 pins available
Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 35 pins available
Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 40 pins available
Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 43 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
Info: The peak interconnect region extends from location X12_Y0 to location X24_Y13
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
Info: Allocated 193 megabytes of memory during processing
Info: Processing ended: Wed Oct 17 12:03:34 2007
Info: Elapsed time: 00:00:08
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
Info: Processing started: Wed Oct 17 12:03:35 2007
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off cpu_top -c cpu_top
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Allocated 149 megabytes of memory during processing
Info: Processing ended: Wed Oct 17 12:03:47 2007
Info: Elapsed time: 00:00:12
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
Info: Processing started: Wed Oct 17 12:03:48 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cpu_top -c cpu_top --timing_analysis_only
Warning: No paths found for timing analysis
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 100 megabytes of memory during processing
Info: Processing ended: Wed Oct 17 12:03:48 2007
Info: Elapsed time: 00:00:00
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
Info: Processing started: Wed Oct 17 12:03:50 2007
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off cpu_top -c cpu_top
Info: Generated file cpu_top.vo in folder "D:/My Project/16bitRISC/without_pipeline/simulation/modelsim/" for EDA simulation tool
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Allocated 96 megabytes of memory during processing
Info: Processing ended: Wed Oct 17 12:03:50 2007
Info: Elapsed time: 00:00:00
Info: Quartus II Full Compilation was successful. 0 errors, 57 warnings
分步编译的详细信息如果需要的话我然后也会贴出来，谢谢了
我刚才把一个模块"pc"的输出pc_address放到顶层的输出端口里面了，然后再综合,发现综合后的“pc”模块占用了逻辑资源，其他的模块还是零占有。感觉QUARTUS在这里是只把跟顶层输出相关的模块给实际例化了，其他的没有输出的模块就没有综合成逻辑器件了，或者说给省略了：（
你的端口声明怎么没有顶层的output阿?
module cpu_test(Clock,nReset,sel8_1,sel8_2,sel3_1,sel4_1,sel2_1,sel2_2,wr_en,inc_SP,dec_SP,inc_pc,load_pc,R_in);
input Clock, nReset;
input [2:0] sel8_1, sel8_2;
input inc_SP, dec_SP,inc_pc,load_pc;
input wr_en;
input [1:0] sel3_1, sel4_1;
input sel2_1, sel2_2;
input [7:0] R_in;
警告里面提示：
Warning: Design contains 27 input pin(s) that do not drive logic
Warning: No output dependent on input pin "Clock"
Warning: No output dependent on input pin "nReset"
Warning: No output dependent on input pin "sel8_1[0]"
Warning: No output dependent on input pin "sel8_1[1]"
Warning: No output dependent on input pin "sel8_1[2]"
Warning: No output dependent on input pin "sel8_2[0]"
Warning: No output dependent on input pin "sel8_2[1]"
Warning: No output dependent on input pin "sel8_2[2]"
Warning: No output dependent on input pin "sel3_1[0]"
Warning: No output dependent on input pin "sel3_1[1]"
Warning: No output dependent on input pin "sel4_1[0]"
Warning: No output dependent on input pin "sel4_1[1]"
Warning: No output dependent on input pin "sel2_1"
Warning: No output dependent on input pin "sel2_2"
Warning: No output dependent on input pin "wr_en"
Warning: No output dependent on input pin "inc_SP"
Warning: No output dependent on input pin "dec_SP"
Warning: No output dependent on input pin "inc_pc"
Warning: No output dependent on input pin "load_pc"
Warning: No output dependent on input pin "R_in[0]"
Warning: No output dependent on input pin "R_in[1]"
Warning: No output dependent on input pin "R_in[2]"
Warning: No output dependent on input pin "R_in[3]"
Warning: No output dependent on input pin "R_in[4]"
Warning: No output dependent on input pin "R_in[5]"
Warning: No output dependent on input pin "R_in[6]"
Warning: No output dependent on input pin "R_in[7]"
对于你所使用的SRAM而言最好是给个初值哈，可以在代码里写一个初值或者使用上电复位实现，上电复位用0时刻提供一个RESET就可以哈，这样的仿真更真实。
Warning (10030): Net "memory.datain[15]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[14]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[13]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[12]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[11]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[10]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[9]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[8]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[7]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[6]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[5]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[4]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[3]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[2]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[1]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.datain[0]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[5]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[4]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[3]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[2]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[1]" at ROM.v(4) has no driver or initial value, using a default initial value 0
Warning (10030): Net "memory.waddr[0]" at ROM.v(4) has no driver or initial value, using a default initial value 0
个人建议你如果给RAM或者ROM写初值的话，最好是随机值，仿真更真实。
因为我顶层是单独的CPU（把ROM和RAM都集成在CPU内部了），所以只有时钟信号和异步复位信号输入，而没有在输出信号了。恩明天尝试把模块独立出来，应该会有些改善（之前写的一个CISC CPU就是把RAM和控制部分分开写的，综合出来系统很能正常），ROM和RAM的初始值的问题我会在INITIAL里面实现的，呵呵谢谢zlmdmeail_80的耐心解答拉
问题就是在你的ROM的写法，initial语句是不能综合的，所以你的ROM在FPGA中实现时必须调用Altera的ROM IP,例如：LPM_ROM,而且指定ROM初始化文件mif或者hex文件，这样才能综合为FPGA内部存储器。initial语句只能用于做仿真时初始化！
恩老师教的时候也说INITIAL部分是不会被综合的但是我在尝试综合的时候发现，其实QUARTUS也会把INITIAL里对RAM或者ROM给的初值在写入综合后生成的器件，这个在我FPGA上跑过了，所以我觉得可能不是这块的问题，不过我还是把RAM和ROM改成异步复位清零的比较好了，更规范。谢谢KARNIZHU的建议哈
因为你没有定义任何的输出管脚, 对P&R来说就没有任何相互之间的依赖关系, 既然没有关系自然就可以优化掉了, 所以P&R之后内部的逻辑全被删除了, 这就是零占用的原因.
恩今天我把程序改了一下，把有判断逻辑和给出控制信号的部分封装到底层模块里面了，在顶层模块只是简单的例化这些底层模块（这样就可以不加输出信号了），综合出来的就可以正确的运行了。以后还是严格的按层次来写。最后谢谢大家的热心建议和帮忙哈
我的也是被完全优化掉了，map viewer看到的只是输入输出，内部没有任何连接。ouput are stuck at GND,input do not drive logic.是因为简单的没有定义输出管脚吗?
你好，jep ！你所说的定义输出管脚是指pin planner还是程序中的ouput啊?
定义输出管脚是指pin planner
语法检查都OK，综合啥咚咚都没有，首先要检查的就应该是自己写的是不是不可综合语句~
还有小编例化咚咚的风格，看着不太习惯我们的都是完全不同的另外一个方式
高深 飘过
学习了……