crossing clock domains of derived clocks？

clock signals clk_12MHZ, clk_6MHZ and clk_3MHZ are derived from clk_48MHZ through synchronous counter, is it necessary to consider the clock-domain-crossing synchronization when communicating data between these clock domains?

不用！
应该是一个时钟域

仍属于同步
有固定相位关系

但是还须后段place&route保证三个时钟之间的skew不能太大。

我也有同一問題, 請問place & route 的 timing constraint 應該如何寫來控制skew?

不敢苟同，lz你从counter出1/x时钟，时钟之间肯定相位差没有特定关系