FPGA中的多时钟域设计

This is not just a theoretical potential. GHz-rate chips with clocking design errors can exhibit the effects of meta-stability quite quickly when running in real systems. These effects typically include loss of critical handshake signals between clocks domains, and corruption of multi-bit data"serious problems that are highly likely to require a chip re-spin.
亚稳态的风险，并不仅仅是理论上的。对于GHz数据率的芯片，如果时钟设计考虑不当，一旦把它放到实际系统中运行，亚稳态的效果所造成的危害很快就会表现出来。最典型的比如说，跨时钟域的关键握手信号丢失，以及并行数据出错。然后这个芯片的设计很可能就泡汤，于是你不得不推倒重来。(所谓 re-spin，按我的理解，是重新开始的意思)

Most designers also know that the textbook solution to meta-stability is using two levels of flip-flops on each signal crossing a clock domain boundary. Even if the first flip-flop does become meta-stable, there is an extremely high likelihood that the signal will settle by the time that it passes through the second level. The double-level flip-flop structure is often called a synchronizer, and designers commonly speak of synchronizing signals across clock domains.
多数设计者都已经知道，对于亚稳态，教科书上经典的解决办法，就是在凡时钟边界的地方，都用两级(D)触发器对信号进行同步。这样的话，哪怕第一级D触发器进入了亚稳态，后一级也极有可能把它克服掉。这种两级触发器结构，通常称为"synchronizer"，这个过程也称为跨时钟域信号同步。

Problem #2: Reset synchronization 复位的同步问题
Improper synchronization of reset signals is a related problem in multi-clock designs. Designers sometimes forget that reset signals are subject to meta-stability and must be protected by synchronizers. Generally, the entire SoC can be reset by a single signal, which therefore must propagate to all clocked elements in all clock domains.
复位信号的不同步，也是一个与多时钟设计相关的问题。设计者有时候会忘了一个事实，那就是复位信号也可能引起亚稳态问题，而且必须用synchronizers来对它进行同步。通常来说，每个SOC都会有一个reset信号，这个信号被送到各个时钟域的各个同步逻辑单元，来对整个芯片/系统进行复位。

There is no need for synchronization on the activation edge of reset, since by definition all state elements are reset to initial values, and the reset signal will generally be held active for enough cycles to allow any meta-stability to settle out.