FPGA中的多时钟域设计

觉得这篇文章很好，因此在这里翻译一下——或者也可以说是按我的理解加中文注释。

MulTIple, independent clocks are ubiquitous in system-on-chip (SoC) design. Most SoC devices have mulTIple interfaces, some following standards that use very different clock frequencies.
在一个SOC设计中，存在多个、独立的时钟，这已经是一件很平常的事情了。大多数的SOC器件都具有很多个接口，各个接口标准都可能会使用完全不同的时钟频率。

Many modern serial interfaces are inherently asynchronous from the rest of the chip; some actually derive their clocks directly from the incoming data streams. There is also a trend toward designing major sub-blocks of SoCs to run on independent clocks to ease the problem of clock skew across large chips.
例如对于现代的串行通信接口而言，它们自然而然地就与芯片的其余部分是不同步的，因为它们的时钟有时候就是直接从数据流中恢复出来的。而且，现在还有一个趋势，就是有时候为了在避免大芯片中令人头痛的所谓"clocl skew"问题，索性让各个子模块都具有独立的时钟。

For all of these reasons, designers working on SoC projects are virtually certain to encounter mulTIple clocks and to be faced with the design of logic interconnecTIng two portions of the chip running on independent clocks. Each such portion is known as a clock domain. The interface between logic on different clocks is called a clock domain crossing or clock domain boundary. The proper handing of signals across clock domain boundaries is critical for successful SoC design.
因为以上原因，进行SOC设计时，常常要考虑工作在不同时钟下的两个部分逻辑之间的互连问题，而每个部分，都可称之为"时钟域"，连接它们之间的那部分数字逻辑可称为"时钟边界"或所谓"跨时钟域"。合理地处理跨时钟的问题，对于一个成功的SOC设计来说非常关键。

Problem #1: Meta-stability

The first multi-clock problem that designers must consider is that of meta-stability as signals pass from one clock domain to another. Most designers understand that meta-stability is a real problem in real circuits; the modern abstractions of RTL design and static timing analysis can't entirely shield designers from having to worry about the underlying physics.
1) 亚稳态
多时钟域设计的第一个问题，便是信号从一个时钟域传输到另一个时钟域的时候，可能会出现亚稳态。 许多设计者都知道，在真实的电路中的确会存在所谓亚稳态的问题。但是，在现代的FPGA设计中，即使设计者面对的是RTL级抽象和静态时序分析，却仍然不能完全将这个问题拒之门外，因为抽象的掩盖之下，我们仍然避免不了真实的物理规律。

Whenever a signal enters a clocked circuit element, such as a flip-flop, too close to the clock, there is the potential for meta-stability. When this happens, the flip-flop may not immediately settle to a known value. It is critical that the output signal from the flip-flop not be used until it has settled.
任何时候，一个信号输入到一个时钟触发的电路——例如一个D触发器，当信号(跳变)过于靠近时钟前沿，便会存在所谓亚稳态问题。这个时候，DFF的输出端不会马上产生一个可预知的值，也就是说，在这段时间内，输出信号是无效的。

On a truly asynchronous clock boundary, the receiving domain's clock is used to capture each signal from the driving domain in a flip-flop. Because there is no defined temporal relationship between the clock and the signal, it is entirely possible that they could transition at the same time. Whenever this happens, there is a possibility of meta-stability in the receiving clock domain.
在设计中，常常会用一个触发器接收来自于另一个时钟域的输出信号(即用本地时钟的前沿来锁存另一个时钟域的信号）。由于触发器的时钟和数据输入信号不存在确定的相位关系，因此完全有可能出现数据和时钟同时跳变的情况。这样，就在接收端所在的时钟域中造成了亚稳态。