玩转赛灵思Zedboard开发板（5）:基于AXI Lite总线的从设备IP设计
_MIN_SIZE => C_S_AXI_MIN_SIZE,
281 C_USE_WSTRB => C_USE_WSTRB,
282 C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
283 C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
284 C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
285 C_FAMILY => C_FAMILY
286 )
287 port map
288 (
289 S_AXI_ACLK => S_AXI_ACLK,
290 S_AXI_ARESETN => S_AXI_ARESETN,
291 S_AXI_AWADDR => S_AXI_AWADDR,
292 S_AXI_AWVALID => S_AXI_AWVALID,
293 S_AXI_WDATA => S_AXI_WDATA,
294 S_AXI_WSTRB => S_AXI_WSTRB,
295 S_AXI_WVALID => S_AXI_WVALID,
296 S_AXI_BREADY => S_AXI_BREADY,
297 S_AXI_ARADDR => S_AXI_ARADDR,
298 S_AXI_ARVALID => S_AXI_ARVALID,
299 S_AXI_RREADY => S_AXI_RREADY,
300 S_AXI_ARREADY => S_AXI_ARREADY,
301 S_AXI_RDATA => S_AXI_RDATA,
302 S_AXI_RRESP => S_AXI_RRESP,
303 S_AXI_RVALID => S_AXI_RVALID,
304 S_AXI_WREADY => S_AXI_WREADY,
305 S_AXI_BRESP => S_AXI_BRESP,
306 S_AXI_BVALID => S_AXI_BVALID,
307 S_AXI_AWREADY => S_AXI_AWREADY,
308 Bus2IP_Clk => ipif_Bus2IP_Clk,
309 Bus2IP_Resetn => ipif_Bus2IP_Resetn,
310 Bus2IP_Addr => ipif_Bus2IP_Addr,
311 Bus2IP_RNW => ipif_Bus2IP_RNW,
312 Bus2IP_BE => ipif_Bus2IP_BE,
313 Bus2IP_CS => ipif_Bus2IP_CS,
314 Bus2IP_RdCE => ipif_Bus2IP_RdCE,
315 Bus2IP_WrCE => ipif_Bus2IP_WrCE,
316 Bus2IP_Data => ipif_Bus2IP_Data,
317 IP2Bus_WrAck => ipif_IP2Bus_WrAck,
318 IP2Bus_RdAck => ipif_IP2Bus_RdAck,
319 IP2Bus_Error => ipif_IP2Bus_Error,
320 IP2Bus_Data => ipif_IP2Bus_Data
321 );
322
323 ------------------------------------------
324 -- instantiate User Logic
325 ------------------------------------------
326 USER_LOGIC_I : component user_logic
327 generic map
328 (
329 -- MAP USER GENERICS BELOW THIS LINE ---------------
330 --USER generics mapped here
331 -- MAP USER GENERICS ABOVE THIS LINE ---------------
332
333 C_NUM_REG => USER_NUM_REG,
334 C_SLV_DWIDTH => USER_SLV_DWIDTH
335 )
336 port map
337 (
338 -- MAP USER PORTS BELOW THIS LINE ------------------
339 LED => LED,
340 -- MAP USER PORTS ABOVE THIS LINE ------------------
341
342 Bus2IP_Clk => ipif_Bus2IP_Clk,
343 Bus2IP_Resetn => ipif_Bus2IP_Resetn,
344 Bus2IP_Data => ipif_Bus2IP_Data,
345 Bus2IP_BE => ipif_Bus2IP_BE,
346 Bus2IP_RdCE => user_Bus2IP_RdCE,
347 Bus2IP_WrCE => user_Bus2IP_WrCE,
348 IP2Bus_Data => user_IP2Bus_Data,
349 IP2Bus_RdAck => user_IP2Bus_RdAck,
350 IP2Bus_WrAck => user_IP2Bus_WrAck,
351 IP2Bus_Error => user_IP2Bus_Error
352 );
353
354 ------------------------------------------
355 -- connect internal signals
356 ------------------------------------------
357 ipif_IP2Bus_Data <= user_IP2Bus_Data;
358 ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
359 ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
360 ipif_IP2Bus_Error <= user_IP2Bus_Error;
361
362 user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
363 user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
364
365 end IMP;
137行
LED : out std_logic_vector(7 downto 0);
定义IP的端口为LED，这里需要和之前修改MPD文件一致。
232-268行为元件声明
1 ------------------------------------------
2 -- Component declaration for verilog user logic
3 ------------------------------------------
4 component user_logic is
5 generic
6 (
7 -- ADD USER GENERICS BELOW THIS LINE ---------------
8 --USER generics added here
9 -- ADD USER GENERICS ABOVE THIS LINE --