玩转赛灵思Zedboard开发板（5）:基于AXI Lite总线的从设备IP设计
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119 -- Bus protocol parameters, do not add to or delete
120 C_S_AXI_DATA_WIDTH : integer := 32;
121 C_S_AXI_ADDR_WIDTH : integer := 32;
122 C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
123 C_USE_WSTRB : integer := 0;
124 C_DPHASE_TIMEOUT : integer := 8;
125 C_BASEADDR : std_logic_vector := X"FFFFFFFF";
126 C_HIGHADDR : std_logic_vector := X"00000000";
127 C_FAMILY : string := "virtex6";
128 C_NUM_REG : integer := 1;
129 C_NUM_MEM : integer := 1;
130 C_SLV_AWIDTH : integer := 32;
131 C_SLV_DWIDTH : integer := 32
132 -- DO NOT EDIT ABOVE THIS LINE ---------------------
133 );
134 port
135 (
136 -- ADD USER PORTS BELOW THIS LINE ------------------
137 LED : out std_logic_vector(7 downto 0);
138 -- ADD USER PORTS ABOVE THIS LINE ------------------
139
140 -- DO NOT EDIT BELOW THIS LINE ---------------------
141 -- Bus protocol ports, do not add to or delete
142 S_AXI_ACLK : in std_logic;
143 S_AXI_ARESETN : in std_logic;
144 S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
145 S_AXI_AWVALID : in std_logic;
146 S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
147 S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
148 S_AXI_WVALID : in std_logic;
149 S_AXI_BREADY : in std_logic;
150 S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
151 S_AXI_ARVALID : in std_logic;
152 S_AXI_RREADY : in std_logic;
153 S_AXI_ARREADY : out std_logic;
154 S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
155 S_AXI_RRESP : out std_logic_vector(1 downto 0);
156 S_AXI_RVALID : out std_logic;
157 S_AXI_WREADY : out std_logic;
158 S_AXI_BRESP : out std_logic_vector(1 downto 0);
159 S_AXI_BVALID : out std_logic;
160 S_AXI_AWREADY : out std_logic
161 -- DO NOT EDIT ABOVE THIS LINE ---------------------
162 );
163
164 attribute MAX_FANOUT : string;
165 attribute SIGIS : string;
166 attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
167 attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
168 attribute SIGIS of S_AXI_ACLK : signal is "Clk";
169 attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
170 end entity my_axi_ip;
171
172 ------------------------------------------------------------------------------
173 -- Architecture section
174 ------------------------------------------------------------------------------
175
176 architecture IMP of my_axi_ip is
177
178 constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
179
180 constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
181
182 constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
183 constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
184 constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
185
186 constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
187 (
188 ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
189 ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
190 );
191
192 constant USER_SLV_NUM_REG : integer := 1;
193 constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
194 constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
195
196 constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
197 (
198 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
199 );
200
201 ----------------------