How to start to design CMOS limiting amp?

I started my Ms Thesis last week, the title is CMOS limiting Amp. but the specification is not clear yet, I just knew I shall design a CMOS limiting amp, software is cadence, 0.13u process. I download about 90 IEEE papers, I am still in reading stage, shall I start to do some cadence exercise first. Can anybody spare your experence with. I really need some suggestion. My question are
1.Shall I design a low power one or high speed one?
2.By using 0.13u process, what is highest freq mydesign can be? I did a project before, it is VCO by using 0.35u process, the highest speed is around 2.7GHz.

Some golden hints!

1. Do not consider old (10years) textbook designs
2. Set a fixed gain for stage ~12dB
3. Mimic a load resistor with a PMOS in linear mode
4. Make shure that the PMOS remain in linear over input range
5. Set up a replicate bias for the PMOS load
6. Use local AC coupling instead of overall DC feedback
7. Alternative use local low frequency integrator feedback instead of AC
8. Design a amplitude detector with current output
9. Summ all currents up to get a RSSI detector

The details of the design are determine by your talent

Some golden hints!

1. Do not consider old (10years) textbook designs
2. Set a fixed gain for stage ~12dB
3. Mimic a load resistor with a PMOS in linear mode
4. Make shure that the PMOS remain in linear over input range
5. Set up a replicate bias for the PMOS load
6. Use local AC coupling instead of overall DC feedback
7. Alternative use local low frequency integrator feedback instead of AC
8. Design a amplitude detector with current output
9. Summ all currents up to get a RSSI detector

The details of the design are determine by your talent


Hi RFsystem:
I am not clear about your reply, would you please give me more detail.
About your reply
1.point No 2. fixed gain for stage. normal is 4 stages, then total gain is about 48dB, is that correct?
2. If use PMOS transistor, the 1/f noise is big problem or not?
3.I don't understood your point 7?