sigma delta carry out

if you want to know what is a sigma-delta ADC,you must know what is sigma delta modulator,here is a paper for the topic.

sigma-delta

sigma=integration
delta =summation/deduction

for ADC, the implementation should be delta-sigma, ->the input signal experience summation(actually deduction) with the feedback signal and the output is than accummulated over time (integration). hence, it is should be called delta-sigma instead of sigma-delta.

for accumulator used in the sigma-delta fractional-N frequency synthesiser,->the input binary code is accumulated first and the final ouput is the carry out which is the result of summation.

the delta-sigma modulator can be thought as continuous-time to discrete-time convertor-> the input signal is continous in amplitude, but the output signal is a sequent of pulse with bianry weigthed. it can also be dc-to-pulse converter, if instantenous time is assumed. as oppose to pll, pulse at charge-pump are converted to dc, with loop filter (low-pass), the input signal are high-pass with delta-sigma modulator.

Delta-sigma modulation is hard to study, I want to design a delta-sigma modulation for PLL, would you please give me some instruction?

I think we maker sure , first , delta-sigma A/D or D/A
use "over sample" & "noise shaping"

we use over sample by modulator (a comparator) and delta-signma
modulator have 1/2/3 ..order ( hi order will unstable but over sample is small , ex. if you use 2 order , you need x256 sample , if you
input signal=1M , you need a 256M clock sample it ,
but if you use 3order , maybe you only need sample x64 ...)

and delta_sigma use modulator convert analog to series "digital"
then use digital_filter (IIR or FIR) make a decimal filter
for down_convert ( usually down 1/4 clock) then use sinC filter

and finally use Biquad filter .

you should know one thing is , delta-sigma have high resolution is average , like 16bit A/D , it provide 16bit bacause SNR have 16bit
not "accuracy 16bit" so we use delta-sigma A/D in audio band
not use for measure signal .... and becuase use DSP implement
filter , analog design is easy in CMOS logic process ...

but as I know , delta-sigma in RF frequency design only for PLL
and use "series digital code for PLL counter"
and conecpt is difference with traditional delta-sigma A/D ...



by the way , who can provide a Matlab code for delta-sigmal mudulator
+filter and give RTL code ? I can not convert matlab code to RTL
equation , who can tell me how to write a "equation by RTL"

thank you