single loop sigma delta modulator design
I found it most simple to use only positive inputs to the SDM. The quantizer at the output is simple feeding the MSBs to the dividers and using the LSBs as error feedback. The filtered LSBs should then be substracted from the SDM input.
The MSB should control a multimodulus divider. So e.g. a 3bit MSB output could control a divider between 64..71.
What do you mean? e.g. a 20bit input, it stands for between 0...1 or 0...7? And when you substract the filtered LSBs, substraction is used, you should use 2's complemenary, and so how to use only positive inputs?
Yes it is true that if the output of the feedback filter is greater in magnitude than the SDM input the result will leave the positive domain. The output of the feedback filter will be limited in magnitude for every sequence of the quantizer feedback. So if the SDM input has a lower bound equal to this maximum value the result will never be negative. So you can use unsigned format for the input and the quantizer (MSB/LSB separation)
Hope that helps.
Hi,rfsystem,but could show me some example.
I do know some single loop sigma delta modulator use MSBs to feedback and throw away LSBs.
And when compare with sigma delta ADC, the feedback signal is the MSB(Δ)?!
Do you mean in MASH?
thanks a lot!
Dear DZC,
I'm designing single loop DSM for PLL block. I have a design example of single loop DSM with MSB feedback loop. I don't understand why they chose MSBs for feedback. Could you explain about that?
Thank you very much !
Hi Bob_lv,
Not sure if you will see this post, since it seems posted pretty long time ago.
I have difficulty to implement a delta sigma type of PLL:
I need 20.625 divide ratio, so I plan to divide VCO frequency first by 10, and then use div2/3 dual modulus divider.
3 stage classic MASH structure is used, and I simulated in simulink, noise spectrum looks fine (with added small dither).
The output of the modulator is within the range of -4 ~ 4, now the question is how to use this info to control dual modulus divider? or should I use multi-modulus divider?
I am reading paper:
"Optimal parameters for single loop Delta sigma modulators".
I am confused on the formula used for SNR and DR (c.f. equation 2 and 3 in the paper ).
The value of SNR does not depend on the value of quantization bits according to the formula. But calculated values of SNR in the Table 1( for one bit quantizer) and table 2(for 4 bit quantizer) show different values of SNR for same valus of oversampling ratio and order of the loop.
I request u to please explain it to me, and suggest any references .
If you want to get 20.625 divider value, and the DSM is MASH 1-1-1. Then your divider must divide from 16~23.
The divider must be a mutimodulus divider. It can be made by a dual-modulus prescaler+P/S Counter or other medthods.