about PLL design for PHS, how to achieve locking time <10

We are try to develop wireless chip for PHS, but seems there is no time slot when switch RX to TX which is about 21MHz, so the locking time for the PLL is very critical, we even don't know 100us is good enough or not.

Anybody can give the suggestion how to design this PLL?

hi lijulia!
we have made a discrete l_band switchable pll by switching time less than 30 us.
Explain me your problem exactly, maybe i can help you.