Do the LNA need the ESD?

时间：04-11 整理：3721RD 点击：

If not, it is easy to failure: if yes, the NF will degenerate .

Shall be finding the compromise that you can live with it.
To minimize the noise degradation tries to integrate the ESD circuit in the NF input match (if the design topology allows this).

A popular solution is using a on-chip spiral shunting to ground node.

Any book or paper has this kind of solution? I also want to know more about this. Thank you.

Yes, I am interested about this also.

RE: Onchip spiral inductor

Don't forget that you might have to handle a spike of tens of amps. It is quick, perhaps a millisecond or so, but you run the risk of vaporizing any on-chip inductor. I have seen hundreds on input shottky diodes vaporized "on-chip" by static, and these were fairly ruged diodes.

You can not beat an off chip series cap, followed by a shunt chip inductor. In severe conditions, you might also want a couple ohms of series resistance.

RF pads without ESD protection exist, but not optimal for high volume production.
Good RF pads don't affect your performance much.

I think the best way to answer is...look to the best LNA factory, namely: Miteq.
Looking inside a Miteq LNA, you'll find ESD protection, usually not on RF input but on the DC lines.
As you certainly know, the electrostatic discharge, that is a fast phenomena, has a spectrum that decrease as the frequency rise (Fourier response of a pulse).
So, most of the ESD energy fall into the lower frequency, and the experience has frequentely shown that the DC line is the critical "gate" for ESD, rather than RF ports.

Protect the DC power supply line of your LNA with a series resistor followed by Zeners or series of Schottky diodes.

We are talking about permanent damage of the pad itself, are we not? I do know that many silicon RF products have ESD. Please comment. Thanks.

I uploaded some papers on the following post, please take a look.

https://www.edaboard.com/viewtopic.php?p=394446#394446

We are talking about permanent damage of the pad itself, are we not? I do know that many silicon RF products have ESD. Please comment. Thanks.

Almost all IC and similar devices such as MMIC , hybrid amplifiers etc use ESD protection diodes to prevent the sensitive circuits ( almost all pin input/output) from ESD discharges.
It should be done as well as to avoid unpredicted performances.

If your technology permits you to put them at input of LNA, double or quadrouple connected diodes will work well.

Some sillicon RF products is not ESD protected in the market nowadays, so they just mark an additional warning in their product datasheet----"Warning! ESD sensitive device". This indicate that they did not put ESD protecting circuit at RF port. If we divide I/O pins into 3 categories -- RF, digital and power pins, we can design proper ESD circuits for digital and power pins as normal circuits. But it is hard to design an ESD for RF pins that did not affect RF performance at all. So just like Sergio said, protect the power line otherwise the IC would be damaged by thunderbolt in a raining day. Digital pins should be protected for the same reason. And as CMOS scaled down to submicron, its thin oxide is easily penetrated by electric shock. Therefore digital line should be ESD protected too.

For RF pins, the perfect ESD solution is still under research. The ESD protecting path is RF->Power line-> outside. So the RF ESD is connected between RF and power pins, and there is additional ESD circuit between Vdd and Gnd.

There are 3 ESD testing standards, one is Human body model, another is Machine mode model, the other..... sorry i forgot :P .... When you try to wirebond your IC to its package leadframe, the bonding maching touches the IC pads directly, so it is the 1st ESD risk to your IC. Next when you get your packaged IC, innocent handling is the 2nd ESD risk. 3rd ESD risk is when you shipping your IC to aboard, 100% fail is possible if you ship your un-ESD IC to the otherside of earth.

There is a special case in IC fabrication phase, we call it "Antenna effect". Namely you can not draw a long wire with open circuit on its ends. The accumulated static charge on the long wire would cause ESD to your device on chip.

The protection that can be achieved using an inductor shunt, alone or with parallel secondary devices are proven. So it will work. There is only one condition, that the inductor should have low resistance, low enough, that the voltage drop during the transient is less than the breakdown voltage of the node being protected. As we the gate oxide layers are becoming thinner, in cmos, the inductor resistance plays a major role. there are a number of patents out there on these methods (ST, Atheros, etc.). The older solution with diodes will not last long..
oxy

To Oxy:

Does that mean the requirement of Q value to on-chip inductor is stringent? Is it possible to make such a inductor under CMOS process with thickend top metal layer?

to dsjomo
Q - as high as possible to avoid RF degradation. yes, thicker back metal formed inductors could do some work..use two or three emplty metal layers and make inductor. but not always possible to use three level. try to use the lowest R inductor. and obviously you have to take into account the C in the matching.
hope this helps, sorry for the delayed replying.

The picture below shows two ESD protection schemes for the LNA input. The left one can withstand HBM of more than 2000V depending on the Resd, but it sacrify NF. The right one, according to the application note of a process, can only pass a HBM of around 1500V. I have used the right one in simulation, the degradation of NF is not very much. So there must be compromise.

I would like to ask: which protection scheme is more common/practical? Is there other practical solution (other than the inductor one).

Dear yolande_yj:

Fewer people use the left ESD proection circuit.

The right one is OK. But its ESD level should be enhanced for production.

Yibin.