Help me design LNA using depletion mode FET process

I am trying to design LNA using depletion mede FET process. can someone help me with this design?

Thanks

the main difference between depletion mode and enhancement mode is the status of the device so
in enhancement mode the device is normally of so u need a gate bais to turn the device on
it is not the case in the depletion mode ,
but u have to check the noise performance of the depeltion mode and the variation with applied voltage