Need help on LNA design

I designed a LNA (inductor source degenerated). Schematic simulationis fine. But in the post layout simulation peak of S21 and min of S11 are always not at the same frequency. Thanks.

In this case you have to use a HPF topology for input matching network, to decrease the gain at low frequencies, and get the maximum S21 for minimum S11.

i think it's not the impedance match thing for the schematic simulation is good, perhaps it's blame for bad layout.

i may sound a bit noobie,but can you explain to me how to give DC source in layout to transistor. You can only see the behaviour of matching network right?

Layout parasiticis have strong influences on circuit performance.That's why, layout should be carefully implemented and the designer should avoid to use strong couplings and long lines etc. on layout.

Second, the models of either active and passive components may not represent "all parasitic embedded" circuits. If models are correct, simulation will also be correct...

hi...but i think my question still remains...how did you activated the transistor in layout ....
I beleive ADS layout do not allow you give DC source ,am I right?
Unless he bring forwards the S parameter of layout back to schematic to simulate...

Hope one of you answer my question too?

I used current mirror biasing the transistor. The mirror is connected to the gate of the transistor through a 50K resistor.

I am using cadence not ADS.