How to design differential PFD?

Now i am designing a PLL. The divider is differential, so I want to design a differential PFD and differential charge pump. Should I first convert the reference signal from the crystal to differential?

what is the normal PLL structure ? differential or single-ended?

Do you use a pure bipolar technology?

Typical asymmetric CMOS provide better PN, power and area trades. Also supply or substrate noise immunity is not perfect under transient condition in symmetric circuits.

If you use CML circuit techniques either in bipolar or NMOS there enough examples for asynchron resetable registers which are the base for PFD.

hello,
using differential CML gives more speed than using CMOS , so u can use fully diffrential CML registers and gate "and" and u have the choice of using fully diffrential Charge pump or diffrential to single-ended topology, noting that using diff. to single is simpler "i think" , while using fully diffrential have a big advantage of noise rejection "power supply and substrate" , this will affect jitter performance. as the control voltage is the most senstive signal in the loop ,so using diffrential Vctrl has very good advantage. of course this will reflect on adding complexty to the loop "like using diffrential VCO".

If i use a differential PFD, how can I get the differential reference signal from a single-ended crystal?