Surge/ESD Protection in RF circuitry

Hi Guys:

When I design the RF circuit, I would include a reversed biased diode model at the I/O port for surge protection. This is illustrated in Figure.1 where a complete I/O model used is presented.

I had received a feedback for an ESD designer to increase the number of series connected diodes to decrease the effective capacitance at the I/O for RF signals, is it advisable to do so?.

I had also received an advise from the foundry to include a p-n junction reversed biased diode at each of the transistor gates in the circuit ad in Figure. 2. Is it advisable to do so?. Would it effect the performance of the designed circuit?.

I highly appreciate your kind assistance. Thanks in advance

Rgds
Harikrishnan

It is OK to use diodes for protection and to use more diodes in series to decrease capacitive loading of input. Disadvantage of using this diodes is higher noise figure.

Thnx for your explanation, it is stated in a foundry design manual an ESD power clamp is required if the capacitance is less than 100nF betweed Vdd and Gnd. Is it possible to avoid this clamp if I place a MOS cap between Vdd and Gnd, with capacitance more than 0.1pF?. Thanks in advance

Rgds