Frequency Divider Design

Hi Guys:

I need some help in the design of the prescaler circuit for my VCO. I find many journals proposing circuit such as ILFD (Injection locked frequency divider) or a commonly used static master-slave flip-flop based frequency didivder. Based on the theory I understand the former architecture relaxes the power consumption requirement. The question is:

1. Does a frequency divider circuit needs to biased in switching mode or inversion mode?.

2. I noticed that, there is a CLK input apart from the D, /D and Q,/Q output, if my frequency of oscillation is 3.5GHz, How much does high does the CLK should oscillates?.

3. In configuring a divide two circuit from a common D master-slave flip-flop, one needs to cross couple two of this flip-flops, to tap the output from the second Q, /Q output (correct me, if it is otherwise). Does this integration require intermediate inverter connection?, Why?.

Your kind assitance is highly appreciated. Thanks in advance

Rgds

To get freq/2 connect D input to (Q not).
In general to get freq/2n connect n f/f in series connecting Q output of one stage to D input of the following stage and connect back (Q not) of last stage to D of first f/f.
Hope that makes sense.

Hi
You will need to connect D to Q_bar and D_bar to Q for the D_FF to get division by two.
There are many architectures for making adivider for such high speed.
1- Static divider
2- Dynamic divider
or they can be viewed as analog based (ILFD and regenerative) and digital based (SCL , TSPC, pesudo, razavi topology, wang topology, dynamic loading)

I am attaching the one that I have implemented