Steps for making a LNA with 1420 MHz, noise factor of 0.5 db and gain above 20 db

hi
i have to make a LNA and specification , frequency = 1420 mhz,noise factor 0.5 db or less and gain will be more than 20 db so i have to use 2 stages amplifier.

can anyone help me and i m a new in this line so i have to start from the beggining.

if anyone have good idea,pls send information in my mailing address.tusha12@yahoo.com.

thanks

u need to implement ur LNA with discreet transistors

check on www.avagotech.com

ATF36163 , it is very low noise , and high gain in the frequency band ur interested in

and also check the appnotes , u will find alot of information

also check www.cel.com
www.nec.com "semiconductor"

khouly

hi
thanks for reply,can u suggest how can i forward step by step.previously i wrote ,i m new in this line and i have to do it this project.

i have to use ads software for reply.

thanks

First : u have to select the transistor , and get the models "S parameter Data" , and nonlinear Model

Second : U need to study the matching concepts

third : u need to match the amp , for stability and minimum Noise Figure

4th : u need to match the output of the Amp for Max power transfer

5th : u need to simulate the Amp in nonlinear mode to get the 1 dB compression point and IIP3 , and so on


check on the help of ADS , and www.rfic.co.uk
and u need to read the gonzalez book "microwave transistor Amplifier analysis and design"

Khouly

my specification
frequency 1.42 GHz
noise figure 0.5 db
gain more than 20

one more thing is that ATF 36163 is stable from over 12 GHz but i have to stabilize that chip for my desired frequency.

can u give any inf about this. if i add resistor into the gate terminal than it will effecit in noise figure so i cant do it . i can add inductor in source side .is it possible.
do u have any idea how can i stable in my desired frequency using any third party software.

thanks

Added after 40 minutes:

hi
sorry, i m distrubing u again. u told me first select the transistor.i select ATF 36163 so its over.
stage 2: i m reading matching concept & also gonzalez book. but problem is that there is a lot of theory.is there any easy tutorial to learn quickly. because i have to solve thia problem by ads.

i have to learn ads software.

thanks

i am not said u must use this transistor , specially , i gave u an example of available transistors.
there are many transistors on avago , cel , u must check them

about the syability u need to read about how to design matching networks for stability
u will find about this issue in gonzalez book

Khouly

hi
i have seen someone use same configuration like me also i saw some tutorial from (http://www.odyseus.nildram.co.uk/RFM...p_tutorial.pdf)this forum but problem is that i dont know how to calculate gain and noise circle in ads.can u give any good tutorial means step by step visual steps in ads.


thanks

i can't give u a detailed step by step
but u check the tutorials on
www.rfic.co.uk
and ask , this will help u alot

khouly

hi
thanks khouly for ur reply.

tusha

hi tusha

if u need any advise , ask , and if u already begin in the design phase , u can send ur schematic and here many ppl can advise u

khouly

hi khouly

thanks for reply.in this forum one person used same like my project and he used ATF 35143 for different Id but my question is , is this transistor is bilateral case or unilateral case for FET.

i have to calculate gain and noise circle for this reason.

thanks

tusha

as far as i know all the real transistors are bilateral , coz the s12 is finite and have small valuse , which effect the design , but in some cases the transistor assumed to be unilateral to simplfy the hand calculation

but u hvae the simulators , so u can work with bilateral , and make the simulator calculate everything

but u need to know , how to use the simulator , and understand what u will do


khouly

Hi khouly

stage 1: i stabilize my transistor add parallel inductance with source side and it stable for my desired frequency.
can u check its right or wrong?

stage 2: after that i designed a input and output matching for 1 transistor this time i configure noise figure and i got 1 series inductance and 1 microstrip line in input matching side and another side i got LC network with 200+j218 with 50
ohms load.
but my question is how i will transfer every components to layout option?


stage 3: actually i have to use 2 transistor so i m using another transistor for gain and stabilkize that 1 and simulate after that i got 50 ohms and 50 ohms so i dont need any matching for this transistor.i m attaching this transistor data and diagram with this file.



stage 4: finally for intermediate matching i add 2 transistor but for second transistor there is no matching network so it will right or wrong.

when u add the second transistor , u have to put a matching network between ur first and second stage
to get the max gain

khouly

hi khouly

sorry for late reply. i was going outside of this city. actually i checked first transistor with 50 ohms source and load and made a input and output matching for one transistor.

when a stabilize first transistor using inductor .it was showing that k is 1 but it should be greater than 1 so i changed the inductance value now its ok.

i choosed first transistor for noise factor and second transistor for gain.

i m checking invidually one by one transistor after that i will add two transistor.

but when i stabilize second transistor and used matching network after that it shows that noise factor is more than 7 . after that i m using optimization techniques for gain and noise factor and i got it but problem is that if i use optimization value for matching circuits in second transistor than maximum value will not transfer from source to load ,i think so.

how can i optimize matching circuits ?


can u tell me anyone who solved our project using two transistor by ads software ?

tusha

what are the transistors ur using ?

about the noise figure of the second stage is 7 , it is very high

and if u design the first stage using 50 ohm source and load , and the second stage using the same 5o ohm source and load then u can cascade the two stages without matching

khouly

hi khouly

i designed two stage LNA by using ATF 35143(2 v ,10 mA) and same transistor (2 v 15 mA).without matching i got following results.

can u check and tell me if it is correct or not.

just i stabilize two transistors by using source inductor 7.1 nH but i havent designed any matching networks for both transistor.even though the result
is showing that overall noise figure .455 dB, MAG is 20 .017 dB and power gain with respect corresponding reflection coefficients is 19.742 dB.

we did all this work by using design guides......amplifiers.....s-parameters
simulations......s-parameters noise...

i m also attaching the results which i got by simulation.

pls check my schemetic diagram and results. iis it ok
or not ?

tusha

dear tusha

the results seems good , but ur design is in linear data , u need to design the bais circuits and so on , also try to match for minmum noise to get better than that , and also for mx gain u can get a better performance of ur amp if u do so

khouly

hi khouly

now i should do optimize my noise figure and gain or what i will do now .

can u explain me in detailes.

or i should taken orginal circuits from datasheet and put in my schemetric.

actually what is my next step?

tusha

Added after 2 minutes:

hi khouly

in my last diagram,i was showing that there was no matching network but my question is , is the transistor correct without matching?


tusha

4 sure it is better to design matching networks , input and output and intermediate

the input should be optimized for minimum noise figure , and the intermediate and output for max output power

the next step to design matching networks , then bias network


khouly