Re: about LNA
last time i created a matching network for individual transistor and i got good noise figure for first transistor.
but problem is that when i made a matching network for second transistor and i got noise figure more than 7 and gain is 20+ after that i optimized noise figure ,gain but it will effect in matching network when i will applied optimize value into the matching network. in this moment , what i will do.
can u try it for me, if u have time.pls.
ATF 35143, 2v 10 mA (1st transistor)
ATF 35143,2v 15mA (2nd transistor)
tusha
hi tusha
i have designed a noise matching network , for the amp
u need to do interstage network
check on the project
so sorry i didn't have much time
khouly
hi khouly
thank you very much..just i opened two stage amp with ADS its showing that MAG is 30.687 db and noise factor is 0.316db.
so we got our specifications without interstage network so do we need to design intermediate stage network. if we dont need then i will go for next step. plz tell me
thank you
tusha
u need to design interstage matching , and also output matching for best performance it could increase the gain to 33 or eveb 35 db , and will not affect the noise figure
so u must design them , and next thing to work with nonlinear model , and make desg the bias network
khouly
hi khouly
with your suggestions i have designed interstage and
output matching networks.but it is showing that NF is
0.8 and MAG is 22.33db.
i have designed these matching networks as follows can
you tell me it is right or not
for 1 st stage (351432d.s2p) i designed input matching
by transforming 50 ohm to (116+j140 which is Zs of
first transistor for min noise figure)
then i designed interstage network network by
trnsforming 12.86+j96.481(which is Zs of first
transistor for max gain) to 9.044+j100.463(which is Zs
of second transistor for max gain)
then i designed output matching network by
transforming 22.08+j173.279 (which is Zl of second
transistor for max gain) to 50 ohm
finally i connected all the designs and simulated.
iam attaching my schematic and result window ...my
humble request is please see my schematic and help me
plz...
tusha
for the intersatge matching
get the output impedance of the frist stage , and get the input impedance of the second stage , and design ur matching network as the Zout of frist stage is the source and the Zin of the second stage is the load
and then the output matching is done for max power
khouly
hi khouly
i designed intermediate and output matching networks
according to your suggestion my results are in
attached file finalamp_result file....so please see
the result file and schematic file and tell me is it
ok or not.
tusha
it is clear that ur ouput matching network is not working good
but the input and interstage is working ok
coz S22 must be at most -8 , so try to modify the output matching
khouly
hi khouly
i tried to design output matching but it is showing that S22 is not getting more than -1.5...so can you design it plz... if you have time actually i have to submit it in next month in my university. so can you do it for me. if i submit this project then i will get my masters. so kindly accept my request.
tusha
hi tusha or halmstad
i donot know
check the schamtic , and the results i posted
khouly
hi khouly
thank you very much...actually me and halmstad are doing this project but the problem is that we dont have perfect knowledge so thts why we have taken your help. me and halmstad were divided our work by some parts like bias network and matching like etc but we dont have knowledge so we both are asking questions to you.....sorry. dont mind wrong...
thank you
tusha&halmstad
it is ok
but u both need to read gaonzalez book , it will help u alot much more than me , coz i am aslo still doing my master
khouly
hi khouly
we have to fabrication also so for this our next step is to do the layout for our schematic so can you tell how to do the layout and fabrication.we have to submit this total project with report in next month.so plz give me suggestion that where i will get the information about layout and fabrication.
and also can we use the bias networks those you designed for me
tusha
yes u an use the bias network
to do the layout , u need to use the art work lib , and have the the layout foot prints of the transistor , if u have all these , then u can begin the layout
khouly
first learn the theory of the lna ,then select the process . the process will decide the performance of lna .so you must analysis the process ,learn the process.
What about implementation and parasitics issues of an LNA? Specially if in case of 2.4GHz LNA?
Thank you in advance,
Ahmad,
the parasitics , will be calculated as the microstips connect the components , and also u cnan use EM cosimulation to get these parasitics
khouly