What is the limit for (S(1,1)) value in LNA design?
My goals for the design is gain>10dB[S(2,1))>10dB], noise figure<0.8dB.
I am getting 11.4dB for gain and noise figure=0.778 at 12GHz for my simulation.
My Question is:
1)my simulated input return loss (S(1,1)) is around -8.4dB and the (S(2,2)) around -31dB.
Is my (S(1,1)) value low enough for my LNA to perform efficiently?
What is the limit for (S(1,1)) value in LNA ?
in the LNA , all u want is a very low noise performance , and this hold that u must match the input from minimum noise which is not the matching for bet S11 , S11 will be -20 or -15 if ur matching for max gain
i think it is normal , check ur gain , and noise figure
Khouly
use the balance structure of your LNA and then y can get both good Noise Figure and S11, this is a way to solve this problem
I am getting 11.4dB for gain and noise figure=0.778 at 12GHz while my S11 is -8.4dB and S22 is -31dB for my simulation.
But when i check stability factor at 12GHz in simulation it shows 0.931
1)Will this cause the LNA to fail when it it is tested after fabrication?
2)How am i to increase the stability factor? Must i optimize the S11 to stabilize the LNA?
i hav attachec the .zap file for viewing. I hope u can help me.
to increase the stabilty factor u need some sort of feedback to make the gain less
but now with ur amp , the K factor is less than one , but ur S11 and S22 is less than zero , it will oscillate if the S11 and s22 is larger than zero
but u can add degeneration coil , or a microstirp trance to make th gain less , and so the transistor will be stable
i will check the project
Khouly
1)what is microstrip trance and where should it be implemented?
2)If i were able reach stability factor,k=0.993 in simulation of the LNA( i cant seem to get higher than 1 without sacrificing gain and nf performance) . Would it be enough to be sure it wont oscillate when tested?
usually when u implement the LNA , the measured K factor will be higher , coz of the loss in the trances , also the soldering , and so on
but also u need to be sure that ur LNA will not oscillate with this source and load impedances
Khouly
Actually what will happen if oscillation occurs in a LNA?
Can u pls explain what will happen to the output, gain, nf and s-parameters?
thanks
If your LAN starts to oscillate then its not an amplifer, its an osciallator beahaviour--which is not desireble in amplifier design.
due to feedback and high gain of the transistor , for some load and source termination may oscillate , in the frequency of oscillation u will find the S11 and S22 is larger than 0 dB , so u can increase ur frequency sweep , and check if the LNA will oscillate in a some frequency
Khouly
I really appreciate your reply, thanks. I did as u told and increased my frequency sweep for the LNA simulation and found that at 9GHz the S11 is 3db but the S22 is always below 0dB.
Do you think this will be a problem? My design involves only Ku band range frequency 10.7 to 12.2 Ghz with 12GHz being the frequency tested.
it is ok , also u must add in ur simulation stabilty measure , and stabilty mu analysis this also will tell u about the stability
Khouly
thanks for all ur reply Mr.khouly.
i have done all the simulation and i am getting desired results. i have added a resistance at the load to improve stability.My design is 12GHz microstrip LNA with gain 10dB and nf 0.77 using ATF36077 phemt.
My problem is now the layout. I hav done the layout but i feel my layout(transistor source pin) grounding is not practical because the source pin of the transistor is overlapping the viagnd i used in ADS.
I tried to increase the length of the microstrip before the grounding but this resulted in performance degrade in simulation.
Do u think the overlapping pin over the ground can be a problem during the soldering process and testing the LNA?
Please advise possible solution to this problem as i am still new to designing and fabricating amplifiers.i hav attached my zap file(12GHz_FR4_3.dsn) for viewing. thanks a lot