LNA input impedance

Hello everybody,

I have a CMOS LNA and the topology is the classic cascode architecture with inductor degeneration at source of input device. what I find is that I can see a negative Z11 (real part) after the S-parameter analysis. Have anybody met the same problem? how come the real part become the negative? what's the physical meaning?

Thanks !

BTW, this is with 65nm technology.

nxing

Hi,

You work with an advanced technology, It's new thing for me to know that. Can I ask you about input polarization transistor. May be , you have problem with Vg ?!

yakeen

this means that the LNA is oscillating , negative S11 means that the LNA is not stable ,

u need to check the stability factor of the LNA , and check source and load stability circils

khouly

Thanks for the reply, guys.
For Yakeen:
I don't see any problem with Vg, also, this is not a close loop.
For Khouly:
Actually, I check the stability factor and it's larger than 1 everywhere.

Any other suggestions?

Thanks

it is strange , S11 is - and the stabilyt factor is larger than 1

can u send the schematic

khouly

I agree with you khouly, non stability cause negative impedance

yakeen

Hi Khouly,
Sorry, the stability factor is actually less than one, indicating unstability. I just wondering what is the cause of this unstability, what I found is that if I lower the OUTPUT inductor's Q, the stability factor increased. Also I found that the Cgs of this technology is very small. So what I do is to put a C parallel with Cgs to slow it down. I didn't see other people use this technique. So far the simulation goes quite well, just not sure there are any drawback for this design or any potential problem.

Regards,

nxing

mmm , it make sense now , specially that the stability factor is less than one

about the Q of the inductor as u lower the serise resistance increase ans this make the Amp more stable, u need to check gonzalez book , he talked about stablization

also check chapter 2 of practical RF circuit design for modern wirless systems VOl II , it is very interesting about stabilization as well

u need to verify the capactiace by simulation , also check the process corners and check if the capaciatnce have been changed what will happen for the stability

khouly

Hey, I too had the same problem in my design. But my cascoding helped me out. Check your values of Cgs, Cgd of the input transistor. If the gain of your transistor is large, chances are your calculated unity-gain frequency is not the right one, in which case, your Ls is not matched to 50 ohms. If that is so, the presence of a reactive element at the source, may result in seeing a negative resistance from the gate. actually Thomas Lee's book on CMOS RF IC design has a problem based on this...

cascodig mimimize the miller effect of th cgd of the input mos trnasisotr , by providing anothe mos betweent the output and input , so this will minimize the effect of the feedback which may make the amp unstable

khouly