help in LNA design urgently

I want to make my LNA is imune to process variationg and i also would like to know how to design the bias circuitry needed for the lna, i'm desigining a normal cs ind degen lna and i'm modifiying it right now according to the paper of asgaran
TO ilminate the soruce inductor to increase the gain

can any on help me with the process imunity and the bias circuitry urgently as i might need to finish the whole design before the start of november :(
any help references, papers, websites , simple words will be appreciated

visit this for LNA design tutorial ..

http://www.zen118213.zen.co.uk/RFIC_Circuits_Page.htm

i don't have any idea for the design against process variations.

deepak

the bias circuit should be nice bandgap refernce ,

which will bias the gate of the CS stage .

check the Lectures of MIT
http://ocw.mit.edu/OcwWeb/Electrical...otes/index.htm

khouly

try using shunt feedback (if u have enough gain), this will not only improve ur return loss but will also make ur active device less sensitive to process variations.

Added after 1 minutes:

try using shunt feedback (if u have enough gain), this will not only improve ur return losses but will also make ur device less sensitive to process variations.