ADIsimPLL VCO tuning law problems

Im using the crystek VCO model number CVCO55BE-2100-2300 for a PLL design.

The tuning voltage is: .3V(min) and 4.7V(max)
The frequency is: 2100MHz(min) and 2300MHz(max)
The tuning sensitivity is: 60 MHz/V
Phase Noise @ 10kHz offset is: -103dBc/Hz

In ADIsimPLL I have to enter the following parameters for the VCO:
Kv=60, V1=.3V, F1=2068MHz , V2 = 4.7, F2 =

To determine F1 I used the following formula:

F1=f(V0)+kV*(V1-V0) = 2068MHz

where f(V0) = 2200MHz
where (kV) = 60 MHz/V
where V1= .3V
where V0 = 2.5Volts


To determine F2 I used the following formula:

F2=f(V0)+kV*(V2-V0) = 2332MHz

where f(V0) = 2200MHz
where (kV) = 60 MHz/V
where V1= 4.7V
where V0 = 2.5Volts

Ok so I place all of the necessary values into ADIsimPLL and I get some erroneous graphs in the time domain. SOmething tells me that this is not right. My question is what is wrong with my lock detect output graph. Why does it look like this? same question for the |freq error| graph(see attachment)

Hi,

Kv should be, 1V @ 2100MHz to 4.5V @ 2300MHz = 60MHz/V.

Also, why is your design freq @ 2441MHz with the doubler enabled?

please show how you derived your answer.

please tell me what you think it should be. This value was given to me by the software. I did not enter this as a parameter.

Q1:
The datasheet shows the Kv plot.


Q2:
I think the doubler is okay, but you need to choose a frequency within the operating freq range on the VCO or else it will never reach lock.

I may be wrong, but I just designed a sythesizer using Crystek VCO's using SIMPLL and did not see any lock problems .

Good luck.


Rod