To simulate I-PMOS C-V Charateristics in cadence

i don't know anything in cadence., but i need to simulate I-PMOS C-V Charateristics in cadence .
so please help , what i have to do


In I-PMOS the bulk connected to gnd and S and D connected together and then to one source . one source is connected between G and gnd . then how to vary Vds. where is Vds ?
can u please tell me the whole steps in cadence.
i have to get capacitance range in pF , while the control voltage range is -2v to 2v., In between 0 to 1 v i have to get -ve linear region.,
please send me reply as soon as possible.,



thanks in advance