Ground in integrated circuits
I′m new in IC design. I will work with RF/MW IC. I would like to know about the ground implementation in an integrated circuit. Most of time, transmission line are CPW. So, if the metal layer used to make the transmission lines is not at the top of the circuit, it needs to be connected with vias. For a microstrip line, it′s the same thing, the ground plane will be connected to circuit ground with vias. I imagine it exists a lot of rules to follow to have a good ground. Could someone tell me the things to do and not to do please or at least a good reference ?
Thanks,
wighou
Bottom side of the MMIC substrate is plated with metal and that's why it's possible to realize some distributed components such as MS Line, CPW etc.This metal plated substrate is place togrounded DIEPAD or PACKAGE PADDLE that is also grounded.
And also, there are few types of GND VIAS called as BACKSIDE VIA and inter metal vias to connect the metal layers to each other.
In the CPW case for example, the metal layer used to make the line and GND is connected to metal plated substrate by these backside vias ? The form factor may be really huge. For a substrate of 300 um of thickness, it means that the backside via is 300 um long and few um large. Is it possible to etch this ? The parasitic inductance may be really high too .
MMIC GaAs substrate thicknesses can not be more than 100um, therefore inductance value of a Backside VIA is around 0.15nH or less..
Interesting. Thank you BigBoss.
But I think I don′t have access to such vias with the process I use (IBM CMOS 0.13um). And the thickness of the substrate is 300um. In this case, do you know how to connect the ground ?
If you use Bipolar/CMOS process, these vias are not available with them.They are only available with GaAs and compound semiconductor processes.
For ground connection of 300um or thicker wafers, you should use down-bonding.I mean, ground connections are done by connecting to paddle or die-pad by bonding wires.But with down-bonded ground connections don't permit you to reach through very high frequencies.Therefore most of RFIC circuits are symmetrical because of common grounding benefits.
But recent developments show us that backside via may be possible with some etching techniques that are extremely expensive for the time being.Because etching 300 um or more is time consuming and makes the wafer fragile.
In your silicon RFIC technology, the bottom of the substrate is far away (substrate thickness is big compared to the on-chip dimensions) and you have the lossy silicon between your metal layers and that "ground" at the bottom of the substrate. In other words, that "ground" at the bottom of the substrate is not useful for building on-chip transmission lines: too far away and very lossy substrate.
For your transmission lines, you want to use the metal + oxide layers above the silicon, and minimize coupling to the lossy substrate. Ground is what you use for ground/return, so you can create your own ground/return path on the metal layers: just think of coplanar with ground-signal-ground or differential lines. Some people also build microstrip structures where they insert a ground shield at one of the bottom metal layers. However, big solide metal planes are not allowed in most cases, so there will be some process dependent tricks to comply with the design rules.
OK, so, in this case, ground wire or ground shield have to be connected to the die′s surface using vias. The strategy is to use the biggest quantity of via possible, isn′t it ?
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It exists a lot of publications of circuits that works at 50 GHz and more in a CMOS process similar to the process I use. How is the ground connection made ?
Could you explain what are the benefits of common grounding please ? Does it mean that differential circuits don′t need a ground physically connected to the output ?