关于TMAX32产生的STIL文件的仿真问题。 $STILDPV

大家好。
我用TMAX32产生了SCAN PATTERN 。
我希望能仿真一下。
但是不知道用什么工具可以做到。
使用了ncverilog modelsim，这两个工具
都不认识下面这段TMAX产生的代码，尤其是里面的任务。
在用modelsim仿真的时候，总是说在0ps的时候达到了迭代极限，自动停止了。
请大家帮帮忙

///*
// STIL Direct Pattern Validate Access
initial begin
//
// --- establish a default time format for %t
//
$timeformat(-9,2," ns",18);
vector_number =5;// 0;
//
// --- default verbosity to 0; use '+define+tmax_msg=N' on verilog compile line to change.
//
`ifdef tmax_msg
verbose = `tmax_msg ;
`else
verbose = 0 ;
`endif
//
// --- default pattern reporting interval is every 5 patterns;
//use '+define+tmax_rpt=N' on verilog compile line to change.
//
`ifdef tmax_rpt
report_interval = `tmax_rpt ;
`else
report_interval = 5 ;
`endif
//
// --- support generating Extened VCD output by using
//'+define+tmax_vcde' on verilog compile line.
//
`ifdef tmax_vcde
// extended VCD, see Verilog specification, IEEE Std. 1364-2001 section 18.3
if (verbose >= 1) $display("// %t : opening Extended VCD output file", $time);
$dumpports( dut, "sim_vcde.out");
`endif
//
// --- default miscompare messages are not formatted for TetraMAX diagnostics;
//use '+define+tmax_diag=N' on verilog compile line to format errors for diagnostics.
//
`ifdef tmax_diag
diagnostic_msg = `tmax_diag ;
`else
diagnostic_msg = 0 ;
`endif
// '+define+tmax_parallel=N' on the command line overrides default simulation, using parallel load
//with N serial vectors at the end of each Shift
// '+define+tmax_serial=M' on the command line forces M initial serial patterns,
//followed by the remainder in parallel (with N serial vectors if tmax_parallel is also specified)
// +define+tmax_par_force_time on the command line overrides default parallel check/load time
`ifdef tmax_par_force_time
$STILDPV_parallel(,,,`tmax_par_force_time);
`endif
// TetraMAX parallel-mode simulation required for these patterns
`ifdef tmax_parallel
// +define+tmax_serial_timing on the command line overrides default minimal-time for parallel load behavior
`ifdef tmax_serial_timing
`else
$STILDPV_parallel(,,0); // apply minimal time advance for parallel load_unload
// if tmax_serial_timing is defined, use equivalent serial load_unload time advance
`endif
`ifdef tmax_serial
$STILDPV_parallel(`tmax_parallel,`tmax_serial);
`else
$STILDPV_parallel(`tmax_parallel,0);
`endif
`else
`ifdef tmax_serial
// +define+tmax_serial_timing on the command line overrides default minimal-time for parallel load behavior
`ifdef tmax_serial_timing
`else
$STILDPV_parallel(,,0); // apply minimal time advance for parallel load_unload
// if tmax_serial_timing is defined, use equivalent serial load_unload time advance
`endif
$STILDPV_parallel(0,`tmax_serial);
`else
// default serial mode
`endif
`endif
if (verbose>3)$STILDPV_trace(1,1,1,1,1,report_interval,diagnostic_msg); // verbose=4; + trace each Vector
else if (verbose>2) $STILDPV_trace(1,0,1,1,1,report_interval,diagnostic_msg); // verbose=3; + trace labels
else if (verbose>1) $STILDPV_trace(0,0,1,1,1,report_interval,diagnostic_msg); // verbose=2; + trace WFT-changes
else if (verbose>0) $STILDPV_trace(0,0,1,0,1,report_interval,diagnostic_msg); // verbose=1; + trace proc/macro entries
else$STILDPV_trace(0,0,0,0,0,report_interval,diagnostic_msg); // verbose=0; only pattern-interval
$STILDPV_setup( "E:/simulation_stil/GPS_DSP_m4_20090617_artisan_ins_scan.stil",,,"GPS_DSP_test.dut" );
while ( ！$STILDPV_done()) #($STILDPV_run( pattern_number, vector_number ));
$display("Time %t: STIL simulation data completed.",$time);
$finish; // comment this out if you terminate the simulation from other activities
end
// STIL Direct Pattern Validate Trace Options
// The STILDPV_trace() function takes '1' to enable a trace and '0' to disable.
// Unspecified arguments maintain their current state. Tracing may be changed at any time.
// The following arguments control tracing of:
// 1st argument: enable or disable tracing of all STIL labels
// 2nd argument: enable or disable tracing of each STIL Vector and current Vector count
// 3rd argument: enable or disable tracing of each additional Thread (new Pattern)
// 4th argument: enable or disable tracing of each WaveformTable change
// 5th argument: enable or disable tracing of each Procedure or Macro entry
// 6th argument: interval to print starting pattern messages; 0 to disable
// For example, a separate initial block may be used to control these options
// (uncomment and change time values to use):
// initial begin
//#800000 $STILDPV_trace(1,1);
//#600000 $STILDPV_trace(,0);
// Additional calls to $STILDPV_parallel() may also be defined to change parallel/serial
// operation during simulation. Any additional calls need a # time value.
// 1st integer is number of serial (flat) cycles to simulate at end of each shift
// 2nd integer is TetraMAX pattern number (starting at zero) to start parallel load
// 3rd optional value '1' will advance time during the load_unload the same as a serial
//shift operation (with no events during that time), '0' will advance minimal time
//(1 shift vector) during the parallel load_unload.
// For example,
//#8000 $STILDPV_parallel( 2,10 );
// end // of initial block with additional trace/parallel options
//*/

比较菜，没看懂

好东西啊

主要问题是ncverilog不认识 函数，苦恼，不知道什么工具能支持

write partten 时使用verilog格式，自己可以看懂，工具也能认。

正需要，弄一个来看看。

写出*.v的文件仿真就可以了。这个需要STIL仿真需要调用动态库，比较麻烦

用ncverilog和vcs都可以仿真。你说的问题需要在run文件中添加一项，具体可以到sold里找，具体是哪个忘记了，那里有告诉你怎么设置。

9# snojasper
那个版本的sold里面有介绍呢?我这里只有2000版的

$STILDPV_parallel( 2,10 ); 這個類似于PLI，需要設定，VCS可以認，其他的工具沒試過；

这个得用DESIGN COMPILER的库文件

you can use VCS + PLI (stildpv) simulation
vcs -P <txs>/stildpv/lib/stildpv_vcs.tab <txs>/stildpv/lib/libstildpv.a

学习下

tmax 可以自己产生仿真脚本文件的。

vcs可以做到，在仿真选项里加一个指向tmax的pli选项就可以了

你好，请教一下如何调用STIL动态库~

你好，我现在做扫描链的插入，在做dft_drc的时候，报告找不到tmax32，我现在急用，你能不能给我传一个啊，我的邮箱是jr_zh@126.com，谢谢啦。

你好，请教一下如何调用STIL动态库~

生成stil文件的时候可以选择所需仿真工具产生相应脚本。

thanks for sharing