关于如下的sram 的lib中缺少一个rise delay的定义
时间：10-02
整理：3721RD
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ERROR的描述如下：
**ERROR: (TECHLIB-9067):(block starting at: 1068) Missing rise delay value for the path from pin CLKB to pin QB[127:0] in the cell sadglsmh4h2p16x128m1b1w1c0p0d0t0s10. Path is not generated ...The data in the timing library is incomplete. This can resultin a loss of accuracy during delay calculation.
1068行的描述如下：
1068timing() {
1069related_pin: "CLKB";
1070timing_sense: non_unate;
1071timing_type: rising_edge;
1072sdf_cond: "！LS & TEST1B";
1073when: "！LS & TEST1B";
1074retaining_rise(CELL_UP) {
1075values( " 0.429670,0.461633,0.525391,0.627494,0.887615,0.974320,1.061161",\
1076" 0.441914,0.473878,0.537636,0.637490,0.897610,0.984316,1.071156",\
1077" 0.461955,0.493918,0.557676,0.653849,0.913970,1.000676,1.087516",\
1078" 0.502119,0.534082,0.597840,0.686636,0.946757,1.033462,1.120303",\
1079" 0.615812,0.641905,0.693952,0.780666,1.040786,1.127492,1.214332",\
1080" 0.685750,0.711843,0.763890,0.850604,1.110725,1.197430,1.284270",\
1081" 0.749971,0.776064,0.828111,0.914825,1.174946,1.261651,1.348492");
1082}
1083retaining_fall(CELL_DN) {
1084values( " 0.429670,0.461633,0.525391,0.627494,0.887615,0.974320,1.061161",\
1085" 0.441914,0.473878,0.537636,0.637490,0.897610,0.984316,1.071156",\
1086" 0.461955,0.493918,0.557676,0.653849,0.913970,1.000676,1.087516",\
1087" 0.502119,0.534082,0.597840,0.686636,0.946757,1.033462,1.120303",\
1088" 0.615812,0.641905,0.693952,0.780666,1.040786,1.127492,1.214332",\
1089" 0.685750,0.711843,0.763890,0.850604,1.110725,1.197430,1.284270",\
1090" 0.749971,0.776064,0.828111,0.914825,1.174946,1.261651,1.348492");
1091}
在之前也有了关于cell_rise和cell_fall的定义了：
347timing() {
348related_pin: "CLKB";
349timing_sense: non_unate;
350timing_type: falling_edge;
351sdf_cond: "！LS & TEST1B";
352when: "！LS & TEST1B";
353cell_rise(CELL_UP) {
354values( " 0.578301,0.610916,0.675975,0.784368,1.109519,1.217901,1.326451",\
355" 0.590795,0.623411,0.688470,0.796862,1.122013,1.230395,1.338945",\
356" 0.611245,0.643860,0.708919,0.817312,1.142462,1.250845,1.359395",\
357" 0.652228,0.684844,0.749903,0.858295,1.183446,1.291828,1.400378",\
358" 0.769765,0.802381,0.867440,0.975832,1.300983,1.409365,1.517915",\
359" 0.857188,0.889803,0.954863,1.063255,1.388406,1.496788,1.605338",\
360" 0.937464,0.970080,1.035139,1.143532,1.468682,1.577064,1.685614");
361}
362cell_fall(CELL_DN) {
363values( " 0.578301,0.610916,0.675975,0.784368,1.109519,1.217901,1.326451",\
364" 0.590795,0.623411,0.688470,0.796862,1.122013,1.230395,1.338945",\
365" 0.611245,0.643860,0.708919,0.817312,1.142462,1.250845,1.359395",\
366" 0.652228,0.684844,0.749903,0.858295,1.183446,1.291828,1.400378",\
367" 0.769765,0.802381,0.867440,0.975832,1.300983,1.409365,1.517915",\
368" 0.857188,0.889803,0.954863,1.063255,1.388406,1.496788,1.605338",\
369" 0.937464,0.970080,1.035139,1.143532,1.468682,1.577064,1.685614");
370}
求问大神，这是啥原因呀?
**ERROR: (TECHLIB-9067):(block starting at: 1068) Missing rise delay value for the path from pin CLKB to pin QB[127:0] in the cell sadglsmh4h2p16x128m1b1w1c0p0d0t0s10. Path is not generated ...The data in the timing library is incomplete. This can resultin a loss of accuracy during delay calculation.
1068行的描述如下：
1068timing() {
1069related_pin: "CLKB";
1070timing_sense: non_unate;
1071timing_type: rising_edge;
1072sdf_cond: "！LS & TEST1B";
1073when: "！LS & TEST1B";
1074retaining_rise(CELL_UP) {
1075values( " 0.429670,0.461633,0.525391,0.627494,0.887615,0.974320,1.061161",\
1076" 0.441914,0.473878,0.537636,0.637490,0.897610,0.984316,1.071156",\
1077" 0.461955,0.493918,0.557676,0.653849,0.913970,1.000676,1.087516",\
1078" 0.502119,0.534082,0.597840,0.686636,0.946757,1.033462,1.120303",\
1079" 0.615812,0.641905,0.693952,0.780666,1.040786,1.127492,1.214332",\
1080" 0.685750,0.711843,0.763890,0.850604,1.110725,1.197430,1.284270",\
1081" 0.749971,0.776064,0.828111,0.914825,1.174946,1.261651,1.348492");
1082}
1083retaining_fall(CELL_DN) {
1084values( " 0.429670,0.461633,0.525391,0.627494,0.887615,0.974320,1.061161",\
1085" 0.441914,0.473878,0.537636,0.637490,0.897610,0.984316,1.071156",\
1086" 0.461955,0.493918,0.557676,0.653849,0.913970,1.000676,1.087516",\
1087" 0.502119,0.534082,0.597840,0.686636,0.946757,1.033462,1.120303",\
1088" 0.615812,0.641905,0.693952,0.780666,1.040786,1.127492,1.214332",\
1089" 0.685750,0.711843,0.763890,0.850604,1.110725,1.197430,1.284270",\
1090" 0.749971,0.776064,0.828111,0.914825,1.174946,1.261651,1.348492");
1091}
在之前也有了关于cell_rise和cell_fall的定义了：
347timing() {
348related_pin: "CLKB";
349timing_sense: non_unate;
350timing_type: falling_edge;
351sdf_cond: "！LS & TEST1B";
352when: "！LS & TEST1B";
353cell_rise(CELL_UP) {
354values( " 0.578301,0.610916,0.675975,0.784368,1.109519,1.217901,1.326451",\
355" 0.590795,0.623411,0.688470,0.796862,1.122013,1.230395,1.338945",\
356" 0.611245,0.643860,0.708919,0.817312,1.142462,1.250845,1.359395",\
357" 0.652228,0.684844,0.749903,0.858295,1.183446,1.291828,1.400378",\
358" 0.769765,0.802381,0.867440,0.975832,1.300983,1.409365,1.517915",\
359" 0.857188,0.889803,0.954863,1.063255,1.388406,1.496788,1.605338",\
360" 0.937464,0.970080,1.035139,1.143532,1.468682,1.577064,1.685614");
361}
362cell_fall(CELL_DN) {
363values( " 0.578301,0.610916,0.675975,0.784368,1.109519,1.217901,1.326451",\
364" 0.590795,0.623411,0.688470,0.796862,1.122013,1.230395,1.338945",\
365" 0.611245,0.643860,0.708919,0.817312,1.142462,1.250845,1.359395",\
366" 0.652228,0.684844,0.749903,0.858295,1.183446,1.291828,1.400378",\
367" 0.769765,0.802381,0.867440,0.975832,1.300983,1.409365,1.517915",\
368" 0.857188,0.889803,0.954863,1.063255,1.388406,1.496788,1.605338",\
369" 0.937464,0.970080,1.035139,1.143532,1.468682,1.577064,1.685614");
370}
求问大神，这是啥原因呀?
这是什么阶段操作什么 的log，
通常sram的lib由compiler生成，认为是没有问题的东西
目前有工具能对库进行查询的，主要输入库文件能够查找单元库的合理性和完整性
sram的lib太advance了吧
synopsys的 sram
在EDI里面读入CCS格式的SRAM的lib的时候出现的问题，奇怪的是用PT读这些SRAM一点问题。当然在读入SRAM的lib的时候，有些没有出现这个问题，有些则出现了。当然可能跟Cadence最开始支持的ECSM model的lib有关系，考虑过，是因为工具的bug原因，还是啥的吗?
描述的很模糊，首先dc，pt能否读入这个lib， edi也应该ok的，多换几个，多读几遍看看
这个问题找到答案了吗?
因为只有ccs没有普通库信息。可直接忽略。
能详细说说吗?今天正好碰到这个问题了。不胜感激！