DC插入ICG问题
我用库里面的CKLN/CKLH*(带TEN, 库里面只有带TEN的ICG) ICG cell, 脚本是
set_clock_gating_style -sequential_cell latch \
-positive_edge_logic {integrated:tcb018gbwp7twc_ccs/CKLNQD2BWP7T}
可是DC报错，
Error: The library cell CKLNQD2BWP7T specified for use as an integrated clock gating does not have the correct value for the clock_gating_integrated_cell attribute. The attribute required is latch_negedge.(PWR-192)
哪位大大能帮忙看看哪里出了问题了吗? RTL代码不能这样写? 在线等......
哪位大大能帮帮忙啊，急啊，CKLNQD2BWP7T 在库里面的feature是clock_gating_integrated_cell呀
你command用的是上升沿，但是error information中提示说这个库单元支持下降沿。所以，是用选项的问题。
我没用过DC插，所以不清楚该怎么写。但是就看你这个命令和REPORT，应该是这么回事。你先改一下，再发REPORT出来看看。
sorry,之前错误报告贴错了， command还是相同的command, 错误报告是，
Error: The library cell CKLNQD2BWP7T specified for use as an integrated clock gating does not have the correct value for the clock_gating_integrated_cell attribute. The attribute required is latch_posedge.(PWR-192)
cell CKLNQD2BWP7T 的feature是
dc_shell> report_attribute tcb018gbwp7twc_ccs/CKLNQD2BWP7T
****************************************
Report : Attribute
Design : CLK_GEN
Version: C-2009.06
Date: Tue Dec 11 16:01:14 2012
****************************************
DesignObjectTypeAttribute NameValue
--------------------------------------------------------------------------------
CKLNQD2BWP7TCKLNQD2BWP7Tdesignarea41.708801
CKLNQD2BWP7TCKLNQD2BWP7Tdesigncell_footprintcklnqd1bwp7t
CKLNQD2BWP7TCKLNQD2BWP7Tdesigncell_leakage_power1.046000
CKLNQD2BWP7TCKLNQD2BWP7Tdesignclock_gating_integrated_cell
latch_posedge_precontrol
CKLNQD2BWP7TCKLNQD2BWP7Tdesignhas_pin_internal_powertrue
CKLNQD2BWP7TCKLNQD2BWP7Tdesignebst_processed2
CKLNQD2BWP7TCKLNQD2BWP7Tdesignebst_validtrue
CKLNQD2BWP7TCKLNQD2BWP7Tdesignfunction_idunknown
CKLNQD2BWP7TCKLNQD2BWP7Tdesignfunction_classunknown
CKLNQD2BWP7TCKLNQD2BWP7Tdesigncmog_classunknown
CKLNQD2BWP7TCKLNQD2BWP7Tdesignmultiple_output_gatetrue
CKLNQD2BWP7TCKLNQD2BWP7Tdesignnumber_of_pins4
CKLNQD2BWP7TCKLNQD2BWP7Tdesignhas_receiver_modetrue
还有个问题，我即使不用ICG，DC也不能综合出latch+gate，所以我在想是不是RTL不能这样写?
我们一般都是直接把ICG例化进来的。
啊，GOD，
直接在RTL里例化
CKLN*U1 （......）;?
Error: The library cell CKLNQD2BWP7T specified for use as an integrated clock gating does not have the correct value for the clock_gating_integrated_cell attribute. The attribute required is latch_posedge.
set_clock_gating_style -sequential_cell latch \
-positive_edge_logic {[color=Red
integrated:tcb018gbwp7twc_ccs/CKLNQD2BWP7T}
你在命令里面指定为positive_edge_logic ，但是指定lib_cell的时候用的是下降沿的icg。其中一个改一下就好了。
如果用 compile_ultra -gate_clock 去插入clock gating 的话，RTL 描述应该如下：
always@（negedge rst_n or posedge clk_in）
if(！rst_n)
A<=1'b0;
else if(clk_en)
A<=B;
DC 会自动帮你把DFF D端的clk_en信号移到CK端的门控。
如果你非要自己用“assign clk_out = clk_en & clk_in;” 加门控的话，需要先编译一遍，然后用
replace_clock_gates + 增量编译
替换掉这个门控
icfb能给解决这个问题么
什么意思?没大明白，用assign就不能直接综合成门控么?
9楼的回答是正确的。这个问题，做过设计的人再去做综合很容易明白。
CKLNQD2BWP7T 的属性：latch_posedge_precontrol
set_clock_gating_style 命令中需要增加-control_point before选项，即可让DC认出。希望能帮到你