关于create_clock和create_generate_clock问题？

做cts的时候有区别

我知道有区别，但是，我不知道有什么区别。

clock source latency 传播不一样

您好，还有其他方面的区别吗?谢谢。

《Static Timing Analysis for Nanometer Designs A Practical Approach》
J. Bhasker • Rakesh Chadha
Page 190 ~ 191
Can a new clock, that is, a master clock, be defined at the output of the flipflop instead of a generated clock? The answer is yes, that it is indeed possible. However, there are some disadvantages. Defining a master clock instead of a generated clock creates a new clock domain. This is not a problem in general except that there are more clock domains to deal with in setting up the constraints for STA. Defining the new clock as a generated clock does not create a new clock domain, and the generated clock is considered to be in phase with its master clock. The generated clock does not require additional constraints to be developed. Thus, one must attempt to define a new internally generated clock as a generated clock instead of deciding to declare it as another master clock.
Another important difference between a master clock and a generated clock is the notion of clock origin. In a master clock, the origin of the clock is at the point of definition of the master clock. In a generated clock, the clock origin is that of the master clock and not that of the generated clock. This implies that in a clock path report, the start point of a clock path is always the master clock definition point. This is a big advantage of a generated clock over defining a new master clock as the source latency is not automatically included for the case of a new master clock.
评论：
两种方式来定义gen_clk都是可行的，但是采用create_clock并不是最佳方案。1，因为无法继承master clock的属性，不利于分析时钟结构；2，在STA过程中，无法看到gen_clk的原始来源，不利于debug timing。
因此，建议，甚至强制要求所有应该用generated_clock进行定义的地方都这么定义。
详情请去仔细看书！
Thanks & Regards,
Joemool

您好，昨天在ICC是试过了，generated clock可以继承master clock的latency，但是，不能继承uncertainty和transition信息。

具体的情况，自己去做实验吧。

找这本书来好好研究一下。

小编公布下答案呗！

都可以， generated clock更多的描述和master clockd的关系
在cts的时候，如果不控制， icc缺省会balance master/generated clock latency ,
如果觉得效果不好，可以自己改成master clock，做完后posctcts 改回来，

都可以， generated clock更多的描述和master clockd的关系
在cts的时候，如果不控制， icc缺省会balance master/generated clock latency ,
如果觉得效果不好，可以自己改成master clock，做完后posctcts 改回来，

有关于create_clock -add的应用讲解吗?

-add - If two create_clock assignments are applied to the same target, the second assignment will be ignored and a warning will be issued.This option on the second assignment
means that it describes a second clock coming into the device.An example where this is used is
if a device plugs into two different boards, and the legacy board might drive a slower clock into
the FPGA.This allows TimeQuest to analyze both scenarios.
add意思简单说就是再让timequest分析一条时钟。当你fpga换主时钟代码没变，可以用这个

小编弄明白了分享一下，在线等

请教大家 用create_generate_clk时，当source时钟和target时钟频率不一致时，-phase指的是谁的相位

generated clk