求助做时序仿真时怎样反标注sdf文件

请教大家，做综合后或布图后的时序仿真时，怎样把生成的sdf文件反标注到仿真工具里，比如Verilog_XL 、VCS 和NC_Verilog，是用什么命令反标还是怎样反标?
请大家给出宝贵的经验！先谢谢了！

直接引用进来就可以。看看具体的工具的manual

写得不错，顶一下！

反标是哪个环节的呢?

$sdf_annotate (“xxx.sdf”, aaa)；
aaa为顶层实例化名

back-annotate，建议看下Advanced chip synthesis，看下ASIC设计flow，

不知何为反标

Separate Annotations
----------------------
This example shows separate annotations to distinct portions of a design hierarchy. There is
no configuration file specification, so the SDF Annotator uses the defaults.
module top;
•••
cpu m1(i1,i2,i3,o1,o2,o3);
fpu m2 (i4,o1,o3,i2,o4,o5,o6);
dma m3(o1,o4,i5,i6,i2);
// perform annotation
initial
begin
$sdf_annotate("cpu.sdf",m1,,"cpu.log");
$sdf_annotate("fpu.sdf",m2,,"fpu.log");
$sdf_annotate("dma.sdf",m3,,"dma.log");
end
// stimulus and response-checking
•••
endmodule
Annotation with Arrays of Instances
------------------------------------
This example shows arrays of instance in a design hierarchy. There is no configuration file
specification, so the SDF Annotator uses the defaults.
module top;
•••
cpu ar[1](i1,i2,i3,o1,o2,o3);
fpu ar[2](i4,o1,o3,i2,o4,o5,o6);
dma ar[3](o1,o4,i5,i6,i2);
// perform annotation
initial
begin
$sdf_annotate("cpu.sdf",ar[1],,"cpu.log");
$sdf_annotate("fpu.sdf",ar[2],,"fpu.log");
$sdf_annotate("dma.sdf",ar[3],,"dma.log");
end
// stimulus and response-checking
•••
endmodule

你好，我是个新手，想请教你一个问题：我在做完延时反标后，再打开波形图后，timing report 上的延时信息并不能全部对应在波形图上，有的对，有的不对，这是为什么啊?我要怎么解决这个问题啊?